gollstt.tan.rpt

实现FPGA的加密程序

; Slack ; Required tsu ; Actual tsu ; From  ; To                 ; To Clock ;
+-------+--------------+------------+-------+--------------------+----------+
; N/A   ; None         ; 2.900 ns   ; done2 ; pres_s.state_bit_1 ; clk      ;
; N/A   ; None         ; 2.900 ns   ; done2 ; pres_s.state_bit_0 ; clk      ;
; N/A   ; None         ; 2.900 ns   ; done1 ; pres_s.state_bit_1 ; clk      ;
; N/A   ; None         ; 2.900 ns   ; done1 ; pres_s.state_bit_0 ; clk      ;
+-------+--------------+------------+-------+--------------------+----------+


+-------------------------------------------------------------------------------+
; tco                                                                           ;
+-------+--------------+------------+--------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From               ; To      ; From Clock ;
+-------+--------------+------------+--------------------+---------+------------+
; N/A   ; None         ; 6.000 ns   ; pres_s.state_bit_1 ; cmp_ena ; clk        ;
; N/A   ; None         ; 6.000 ns   ; pres_s.state_bit_0 ; cmp_ena ; clk        ;
; N/A   ; None         ; 6.000 ns   ; pres_s.state_bit_1 ; ena     ; clk        ;
; N/A   ; None         ; 6.000 ns   ; pres_s.state_bit_0 ; ena     ; clk        ;
+-------+--------------+------------+--------------------+---------+------------+


+---------------------------------------------------------------------------------+
; th                                                                              ;
+---------------+-------------+-----------+-------+--------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To                 ; To Clock ;
+---------------+-------------+-----------+-------+--------------------+----------+
; N/A           ; None        ; -1.000 ns ; done2 ; pres_s.state_bit_1 ; clk      ;
; N/A           ; None        ; -1.000 ns ; done2 ; pres_s.state_bit_0 ; clk      ;
; N/A           ; None        ; -1.000 ns ; done1 ; pres_s.state_bit_1 ; clk      ;
; N/A           ; None        ; -1.000 ns ; done1 ; pres_s.state_bit_0 ; clk      ;
+---------------+-------------+-----------+-------+--------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Aug 14 22:23:11 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off gollstt -c gollstt
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 227.27 MHz between source register "pres_s.state_bit_1" and destination register "pres_s.state_bit_1" (period= 4.4 ns)
    Info: + Longest register to register delay is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'
        Info: 2: + IC(0.900 ns) + CELL(1.500 ns) = 2.400 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'
        Info: Total cell delay = 1.500 ns ( 62.50 % )
        Info: Total interconnect delay = 0.900 ns ( 37.50 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Micro setup delay of destination is 1.300 ns
Info: tsu for register "pres_s.state_bit_1" (data pin = "done2", clock pin = "clk") is 2.900 ns
    Info: + Longest pin to register delay is 3.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_15; Fanout = 3; PIN Node = 'done2'
        Info: 2: + IC(0.900 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'
        Info: Total cell delay = 2.200 ns ( 70.97 % )
        Info: Total interconnect delay = 0.900 ns ( 29.03 % )
    Info: + Micro setup delay of destination is 1.300 ns
    Info: - Shortest clock path from clock "clk" to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "cmp_ena" through register "pres_s.state_bit_1" is 6.000 ns
    Info: + Longest clock path from clock "clk" to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Longest register to pin delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'
        Info: 2: + IC(0.900 ns) + CELL(2.100 ns) = 3.000 ns; Loc. = LC2; Fanout = 1; COMB Node = 'pres_s.st3~20'
        Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 3.800 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'cmp_ena'
        Info: Total cell delay = 2.900 ns ( 76.32 % )
        Info: Total interconnect delay = 0.900 ns ( 23.68 % )
Info: th for register "pres_s.state_bit_1" (data pin = "done2", clock pin = "clk") is -1.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 0.600 ns
    Info: - Shortest pin to register delay is 3.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_15; Fanout = 3; PIN Node = 'done2'
        Info: 2: + IC(0.900 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'
        Info: Total cell delay = 2.200 ns ( 70.97 % )
        Info: Total interconnect delay = 0.900 ns ( 29.03 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 113 megabytes of memory during processing
    Info: Processing ended: Thu Aug 14 22:23:16 2008
    Info: Elapsed time: 00:00:05