gollman.sim.rpt

实现FPGA的加密程序

; |gollman|enad~0          ; |gollman|enad~0          ; combout          ;
; |gollman|srd[2]          ; |gollman|srd[2]          ; regout           ;
; |gollman|sra[2]          ; |gollman|sra[2]          ; regout           ;
; |gollman|srb[2]          ; |gollman|srb[2]          ; regout           ;
; |gollman|always2~0       ; |gollman|always2~0       ; combout          ;
; |gollman|src[2]          ; |gollman|src[2]          ; regout           ;
; |gollman|always3~0       ; |gollman|always3~0       ; combout          ;
; |gollman|srd[3]          ; |gollman|srd[3]          ; regout           ;
; |gollman|sra[3]          ; |gollman|sra[3]          ; regout           ;
; |gollman|srb[3]          ; |gollman|srb[3]          ; regout           ;
; |gollman|src[0]          ; |gollman|src[0]          ; regout           ;
; |gollman|src[2]~136      ; |gollman|src[2]~136      ; combout          ;
; |gollman|srd[4]          ; |gollman|srd[4]          ; regout           ;
; |gollman|sra[4]          ; |gollman|sra[4]          ; regout           ;
; |gollman|srb[0]          ; |gollman|srb[0]          ; regout           ;
; |gollman|srb[3]~151      ; |gollman|srb[3]~151      ; combout          ;
; |gollman|srd[5]          ; |gollman|srd[5]          ; regout           ;
; |gollman|sra[5]          ; |gollman|sra[5]          ; regout           ;
; |gollman|srd[6]          ; |gollman|srd[6]          ; regout           ;
; |gollman|sra[6]          ; |gollman|sra[6]          ; regout           ;
; |gollman|srd[7]          ; |gollman|srd[7]          ; regout           ;
; |gollman|sra[6]~121      ; |gollman|sra[6]~121      ; combout          ;
; |gollman|srd[8]          ; |gollman|srd[8]          ; regout           ;
; |gollman|srd[9]          ; |gollman|srd[9]          ; regout           ;
; |gollman|srd[10]         ; |gollman|srd[10]         ; regout           ;
; |gollman|srd[11]         ; |gollman|srd[11]         ; regout           ;
; |gollman|srd~220         ; |gollman|srd~220         ; combout          ;
; |gollman|srd[0]~221      ; |gollman|srd[0]~221      ; combout          ;
; |gollman|srd[1]~222      ; |gollman|srd[1]~222      ; combout          ;
; |gollman|sra[1]~122      ; |gollman|sra[1]~122      ; combout          ;
; |gollman|src[1]~137      ; |gollman|src[1]~137      ; combout          ;
; |gollman|srd[2]~223      ; |gollman|srd[2]~223      ; combout          ;
; |gollman|sra[2]~123      ; |gollman|sra[2]~123      ; combout          ;
; |gollman|srb[2]~152      ; |gollman|srb[2]~152      ; combout          ;
; |gollman|sra[4]~124      ; |gollman|sra[4]~124      ; combout          ;
; |gollman|srb[0]~154      ; |gollman|srb[0]~154      ; combout          ;
; |gollman|srd[5]~224      ; |gollman|srd[5]~224      ; combout          ;
; |gollman|sra[5]~125      ; |gollman|sra[5]~125      ; combout          ;
; |gollman|srd[6]~225      ; |gollman|srd[6]~225      ; combout          ;
; |gollman|srd[7]~226      ; |gollman|srd[7]~226      ; combout          ;
; |gollman|srd[8]~227      ; |gollman|srd[8]~227      ; combout          ;
; |gollman|srd[10]~228     ; |gollman|srd[10]~228     ; combout          ;
; |gollman|clk             ; |gollman|clk~corein      ; combout          ;
; |gollman|ena             ; |gollman|ena~corein      ; combout          ;
; |gollman|data            ; |gollman|data            ; padio            ;
; |gollman|done            ; |gollman|done            ; padio            ;
; |gollman|iena            ; |gollman|iena            ; padio            ;
; |gollman|enab            ; |gollman|enab            ; padio            ;
; |gollman|enac            ; |gollman|enac            ; padio            ;
; |gollman|enad            ; |gollman|enad            ; padio            ;
; |gollman|clk~clkctrl     ; |gollman|clk~clkctrl     ; outclk           ;
; |gollman|last_ena~feeder ; |gollman|last_ena~feeder ; combout          ;
; |gollman|src[0]~feeder   ; |gollman|src[0]~feeder   ; combout          ;
; |gollman|srb[1]~feeder   ; |gollman|srb[1]~feeder   ; combout          ;
; |gollman|srd[3]~feeder   ; |gollman|srd[3]~feeder   ; combout          ;
; |gollman|sra[3]~feeder   ; |gollman|sra[3]~feeder   ; combout          ;
; |gollman|srd[9]~feeder   ; |gollman|srd[9]~feeder   ; combout          ;
+--------------------------+--------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------+
; Missing 1-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------+
; Missing 0-Value Coverage                                           ;
+------------------------+------------------------+------------------+
; Node Name              ; Output Port Name       ; Output Port Type ;
+------------------------+------------------------+------------------+
; |gollman|reset         ; |gollman|reset~corein  ; combout          ;
; |gollman|reset~clkctrl ; |gollman|reset~clkctrl ; outclk           ;
+------------------------+------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Aug 15 09:49:34 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off gollman -c gollman
Info: Using vector source file "E:/FPGA/FPGA加密/gollman/gollman.vwf"
Info: Overwriting simulation input file with simulation results
    Info: A backup of gollman.vwf called gollman.sim_ori.vwf has been created in the db folder
Info: Inverted registers were found during simulation
    Info: Register: |gollman|donei
    Info: Register: |gollman|srd[1]
    Info: Register: |gollman|sra[1]
    Info: Register: |gollman|src[1]
    Info: Register: |gollman|srd[3]
    Info: Register: |gollman|sra[3]
    Info: Register: |gollman|srb[3]
    Info: Register: |gollman|src[0]
    Info: Register: |gollman|srd[4]
    Info: Register: |gollman|sra[4]
    Info: Register: |gollman|srb[0]
    Info: Register: |gollman|srd[5]
    Info: Register: |gollman|sra[6]
    Info: Register: |gollman|srd[7]
    Info: Register: |gollman|srd[9]
    Info: Register: |gollman|srd[10]
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      97.33 %
Info: Number of transitions in simulation is 804959
Info: Vector file gollman.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 107 megabytes of memory during processing
    Info: Processing ended: Fri Aug 15 09:49:47 2008
    Info: Elapsed time: 00:00:13