📄 prev_cmp_gollman.tan.qmsg

📁 实现FPGA的加密程序
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register iena src\[1\] 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"iena\" and destination register \"src\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.352 ns + Longest register register " "Info: + Longest register to register delay is 2.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iena 1 REG LCFF_X9_Y4_N25 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y4_N25; Fanout = 12; REG Node = 'iena'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iena } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.206 ns) 0.968 ns always3~0 2 COMB LCCOMB_X8_Y4_N30 2 " "Info: 2: + IC(0.762 ns) + CELL(0.206 ns) = 0.968 ns; Loc. = LCCOMB_X8_Y4_N30; Fanout = 2; COMB Node = 'always3~0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.968 ns" { iena always3~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.855 ns) 2.352 ns src\[1\] 3 REG LCFF_X9_Y4_N17 2 " "Info: 3: + IC(0.529 ns) + CELL(0.855 ns) = 2.352 ns; Loc. = LCFF_X9_Y4_N17; Fanout = 2; REG Node = 'src\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.384 ns" { always3~0 src[1] } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.061 ns ( 45.11 % ) " "Info: Total cell delay = 1.061 ns ( 45.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.291 ns ( 54.89 % ) " "Info: Total interconnect delay = 1.291 ns ( 54.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { iena always3~0 src[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { iena {} always3~0 {} src[1] {} } { 0.000ns 0.762ns 0.529ns } { 0.000ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.785 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.836 ns) + CELL(0.666 ns) 2.785 ns src\[1\] 3 REG LCFF_X9_Y4_N17 2 " "Info: 3: + IC(0.836 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X9_Y4_N17; Fanout = 2; REG Node = 'src\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.502 ns" { clk~clkctrl src[1] } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.85 % ) " "Info: Total cell delay = 1.806 ns ( 64.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.979 ns ( 35.15 % ) " "Info: Total interconnect delay = 0.979 ns ( 35.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl src[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk {} clk~combout {} clk~clkctrl {} src[1] {} } { 0.000ns 0.000ns 0.143ns 0.836ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.785 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.836 ns) + CELL(0.666 ns) 2.785 ns iena 3 REG LCFF_X9_Y4_N25 12 " "Info: 3: + IC(0.836 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X9_Y4_N25; Fanout = 12; REG Node = 'iena'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.502 ns" { clk~clkctrl iena } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.85 % ) " "Info: Total cell delay = 1.806 ns ( 64.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.979 ns ( 35.15 % ) " "Info: Total interconnect delay = 0.979 ns ( 35.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl iena } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk {} clk~combout {} clk~clkctrl {} iena {} } { 0.000ns 0.000ns 0.143ns 0.836ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl src[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk {} clk~combout {} clk~clkctrl {} src[1] {} } { 0.000ns 0.000ns 0.143ns 0.836ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl iena } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk {} clk~combout {} clk~clkctrl {} iena {} } { 0.000ns 0.000ns 0.143ns 0.836ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 114 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { iena always3~0 src[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { iena {} always3~0 {} src[1] {} } { 0.000ns 0.762ns 0.529ns } { 0.000ns 0.206ns 0.855ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl src[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk {} clk~combout {} clk~clkctrl {} src[1] {} } { 0.000ns 0.000ns 0.143ns 0.836ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl iena } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk {} clk~combout {} clk~clkctrl {} iena {} } { 0.000ns 0.000ns 0.143ns 0.836ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { src[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { src[1] {} } {  } {  } "" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 114 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "ITDB_TSU_RESULT" "iena ena clk 5.063 ns register " "Info: tsu for register \"iena\" (data pin = \"ena\", clock pin = \"clk\") is 5.063 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.888 ns + Longest pin register " "Info: + Longest pin to register delay is 7.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns ena 1 PIN PIN_35 4 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_35; Fanout = 4; PIN Node = 'ena'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ena } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.144 ns) + CELL(0.651 ns) 7.780 ns always0~0 2 COMB LCCOMB_X9_Y4_N24 1 " "Info: 2: + IC(6.144 ns) + CELL(0.651 ns) = 7.780 ns; Loc. = LCCOMB_X9_Y4_N24; Fanout = 1; COMB Node = 'always0~0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.795 ns" { ena always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.888 ns iena 3 REG LCFF_X9_Y4_N25 12 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.888 ns; Loc. = LCFF_X9_Y4_N25; Fanout = 12; REG Node = 'iena'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { always0~0 iena } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.744 ns ( 22.11 % ) " "Info: Total cell delay = 1.744 ns ( 22.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.144 ns ( 77.89 % ) " "Info: Total interconnect delay = 6.144 ns ( 77.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.888 ns" { ena always0~0 iena } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.888 ns" { ena {} ena~combout {} always0~0 {} iena {} } { 0.000ns 0.000ns 6.144ns 0.000ns } { 0.000ns 0.985ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.785 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.836 ns) + CELL(0.666 ns) 2.785 ns iena 3 REG LCFF_X9_Y4_N25 12 " "Info: 3: + IC(0.836 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X9_Y4_N25; Fanout = 12; REG Node = 'iena'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.502 ns" { clk~clkctrl iena } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.85 % ) " "Info: Total cell delay = 1.806 ns ( 64.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.979 ns ( 35.15 % ) " "Info: Total interconnect delay = 0.979 ns ( 35.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl iena } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk {} clk~combout {} clk~clkctrl {} iena {} } { 0.000ns 0.000ns 0.143ns 0.836ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.888 ns" { ena always0~0 iena } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.888 ns" { ena {} ena~combout {} always0~0 {} iena {} } { 0.000ns 0.000ns 6.144ns 0.000ns } { 0.000ns 0.985ns 0.651ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl iena } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk {} clk~combout {} clk~clkctrl {} iena {} } { 0.000ns 0.000ns 0.143ns 0.836ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data srd\[0\] 7.575 ns register " "Info: tco from clock \"clk\" to destination pin \"data\" through register \"srd\[0\]\" is 7.575 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.784 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.835 ns) + CELL(0.666 ns) 2.784 ns srd\[0\] 3 REG LCFF_X8_Y4_N19 2 " "Info: 3: + IC(0.835 ns) + CELL(0.666 ns) = 2.784 ns; Loc. = LCFF_X8_Y4_N19; Fanout = 2; REG Node = 'srd\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { clk~clkctrl srd[0] } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.87 % ) " "Info: Total cell delay = 1.806 ns ( 64.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.978 ns ( 35.13 % ) " "Info: Total interconnect delay = 0.978 ns ( 35.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clk clk~clkctrl srd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clk {} clk~combout {} clk~clkctrl {} srd[0] {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 135 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.487 ns + Longest register pin " "Info: + Longest register to pin delay is 4.487 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns srd\[0\] 1 REG LCFF_X8_Y4_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y4_N19; Fanout = 2; REG Node = 'srd\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { srd[0] } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.391 ns) + CELL(3.096 ns) 4.487 ns data 2 PIN PIN_34 0 " "Info: 2: + IC(1.391 ns) + CELL(3.096 ns) = 4.487 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'data'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.487 ns" { srd[0] data } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 69.00 % ) " "Info: Total cell delay = 3.096 ns ( 69.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.391 ns ( 31.00 % ) " "Info: Total interconnect delay = 1.391 ns ( 31.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.487 ns" { srd[0] data } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.487 ns" { srd[0] {} data {} } { 0.000ns 1.391ns } { 0.000ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clk clk~clkctrl srd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clk {} clk~combout {} clk~clkctrl {} srd[0] {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.487 ns" { srd[0] data } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.487 ns" { srd[0] {} data {} } { 0.000ns 1.391ns } { 0.000ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "ITDB_TH_RESULT" "enad reset clk -0.288 ns register " "Info: th for register \"enad\" (data pin = \"reset\", clock pin = \"clk\") is -0.288 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.784 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.835 ns) + CELL(0.666 ns) 2.784 ns enad 3 REG LCFF_X8_Y4_N3 1 " "Info: 3: + IC(0.835 ns) + CELL(0.666 ns) = 2.784 ns; Loc. = LCFF_X8_Y4_N3; Fanout = 1; REG Node = 'enad'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { clk~clkctrl enad } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.87 % ) " "Info: Total cell delay = 1.806 ns ( 64.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.978 ns ( 35.13 % ) " "Info: Total interconnect delay = 0.978 ns ( 35.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clk clk~clkctrl enad } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clk {} clk~combout {} clk~clkctrl {} enad {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.378 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns reset 1 PIN PIN_24 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 5; PIN Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.393 ns) + CELL(0.855 ns) 3.378 ns enad 2 REG LCFF_X8_Y4_N3 1 " "Info: 2: + IC(1.393 ns) + CELL(0.855 ns) = 3.378 ns; Loc. = LCFF_X8_Y4_N3; Fanout = 1; REG Node = 'enad'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.248 ns" { reset enad } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.985 ns ( 58.76 % ) " "Info: Total cell delay = 1.985 ns ( 58.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.393 ns ( 41.24 % ) " "Info: Total interconnect delay = 1.393 ns ( 41.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.378 ns" { reset enad } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.378 ns" { reset {} reset~combout {} enad {} } { 0.000ns 0.000ns 1.393ns } { 0.000ns 1.130ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clk clk~clkctrl enad } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clk {} clk~combout {} clk~clkctrl {} enad {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.378 ns" { reset enad } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.378 ns" { reset {} reset~combout {} enad {} } { 0.000ns 0.000ns 1.393ns } { 0.000ns 1.130ns 0.855ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "Classic Timing Analyzer" 0}
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