gollman.vhd

实现FPGA的加密程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY gollman IS
PORT (
clk : IN std_logic;
reset : IN std_logic;
ena : IN std_logic;
data : OUT std_logic;
done : OUT std_logic);
END gollman;
ARCHITECTURE synth OF gollman IS
CONSTANT keya : std_logic_vector(6 downto 0) := "1011011"; -- 1st LFR key
CONSTANT keyb : std_logic_vector(3 downto 0) := "1001"; -- 2nd LFR key
CONSTANT keyc : std_logic_vector(2 downto 0) := "011"; -- 3rd LFR key
CONSTANT keyd : std_logic_vector(11 downto 0) := "011010111010"; -- 4th LFR key
SIGNAL sra : std_logic_vector(6 downto 0); -- 1st LFR instantiation
SIGNAL srb : std_logic_vector(3 downto 0); -- 2nd
SIGNAL src : std_logic_vector(2 downto 0); -- 3rd
SIGNAL srd : std_logic_vector(11 downto 0); -- 4th
SIGNAL enab : std_logic; -- Clock enables for cascade LFRs
SIGNAL enac : std_logic;
SIGNAL enad : std_logic;
SIGNAL last_ena : std_logic; -- Registered 'ena
SIGNAL donei : std_logic; -- internal 'done' node
SIGNAL iena : std_logic; -- internal 'single clock' ena
SIGNAL oena : std_logic; -- registered version of ena - for edge detect
BEGIN
-- Process to edge detect enable signal to generate single clock duration enable
enable: PROCESS(clk,reset)
BEGIN
IF reset = '1' THEN
iena <= '0';
oena <= '0';
ELSIF clk'event AND clk = '1' THEN
oena <= ena;
IF ena = '1' AND oena = '0' THEN
iena <= '1';
ELSE
iena <= '0';
END IF;
END IF;
END PROCESS enable;
-- Implementation of 1st LFR in this cascade
lfr1: PROCESS(clk,reset)
BEGIN
IF reset = '1' THEN
sra <= keya;
ELSIF clk'event AND clk = '1' THEN
IF iena = '1' THEN
sra(5 downto 0) <= sra(6 downto 1); -- Perform Shift
sra(6) <= sra(6) XOR sra(2); -- XOR bits 6,2 for maximal

ELSE
sra <= sra;
END IF;
enab <= NOT sra(1); -- Generate enable for next
-- LFR in cascade
ELSE
sra <= sra;
enab <= enab;
END IF;
END PROCESS lfr1;
-- Implementation of 2nd LFR in this cascade
lfr2: PROCESS(clk,reset)
BEGIN
IF reset = '1' THEN
srb <= keyb;
ELSIF clk'event AND clk = '1' THEN
IF iena = '1' AND enab = '1' THEN
srb(2 downto 0) <= srb(3 downto 1); -- Perform Shift
srb(3) <= srb(3) XOR srb(0); -- XOR bits 3,0 for
-- maximal length
ELSE
srb <= srb;
END IF;
enac <= (NOT sra(1)) XOR srb(1); -- Generate enable for
-- next LFR in cascade
ELSE
srb <= srb;
enac <= enac;
END IF;
END PROCESS lfr2;
-- Implementation of 3rd LFR in cascade
lfr3: PROCESS(clk,reset)
BEGIN
IF reset = '1' THEN
src <= keyc;
ELSIF clk'event AND clk = '1' THEN
IF iena = '1' AND enac = '1' THEN
src(1 downto 0) <= src(2 downto 1); -- Perform Shift
src(2) <= src(2) XOR src(0); -- XOR bits 2,0 for
-- maximal length
ELSE
src <= src;
END IF;
enad <= (NOT sra(1)) XOR srb(1) XOR src(1); -- Generate enable for
-- next LFR in cascade
ELSE
src <= src;
enad <= enad;
END IF;
END PROCESS lfr3;
-- Implementation of 4th LFR in cascade
lfr4: PROCESS(clk,reset)
BEGIN
IF reset = '1' THEN
srd <= keyd;
ELSIF clk'event AND clk = '1' THEN
IF iena = '1' AND enad = '1' THEN
srd(10 downto 0) <= srd(11 downto 1); -- Perform Shift
srd(11) <= srd(11) XOR srd(5) XOR srd(3) XOR srd(0);
-- XOR bits 11,5,3,0 for maximal length
ELSE
srd <= srd;
END IF;
ELSE
srd <= srd;
END IF;
data <= srd(0); -- Assign output
END PROCESS lfr4;

ELSE
sra <= sra;
END IF;
enab <= NOT sra(1); -- Generate enable for next
-- LFR in cascade
ELSE
sra <= sra;
enab <= enab;
END IF;
END PROCESS lfr1;
-- Implementation of 2nd LFR in this cascade
lfr2: PROCESS(clk,reset)
BEGIN
IF reset = '1' THEN
srb <= keyb;
ELSIF clk'event AND clk = '1' THEN
IF iena = '1' AND enab = '1' THEN
srb(2 downto 0) <= srb(3 downto 1); -- Perform Shift
srb(3) <= srb(3) XOR srb(0); -- XOR bits 3,0 for
-- maximal length
ELSE
srb <= srb;
END IF;
enac <= (NOT sra(1)) XOR srb(1); -- Generate enable for
-- next LFR in cascade
ELSE
srb <= srb;
enac <= enac;
END IF;
END PROCESS lfr2;
-- Implementation of 3rd LFR in cascade
lfr3: PROCESS(clk,reset)
BEGIN
IF reset = '1' THEN
src <= keyc;
ELSIF clk'event AND clk = '1' THEN
IF iena = '1' AND enac = '1' THEN
src(1 downto 0) <= src(2 downto 1); -- Perform Shift
src(2) <= src(2) XOR src(0); -- XOR bits 2,0 for
-- maximal length
ELSE
src <= src;
END IF;
enad <= (NOT sra(1)) XOR srb(1) XOR src(1); -- Generate enable for
-- next LFR in cascade
ELSE
src <= src;
enad <= enad;
END IF;
END PROCESS lfr3;
-- Implementation of 4th LFR in cascade
lfr4: PROCESS(clk,reset)
BEGIN
IF reset = '1' THEN
srd <= keyd;
ELSIF clk'event AND clk = '1' THEN
IF iena = '1' AND enad = '1' THEN
srd(10 downto 0) <= srd(11 downto 1); -- Perform Shift
srd(11) <= srd(11) XOR srd(5) XOR srd(3) XOR srd(0);
-- XOR bits 11,5,3,0 for maximal length
ELSE
srd <= srd;
END IF;
ELSE
srd <= srd;
END IF;
data <= srd(0); -- Assign output
END PROCESS lfr4;