gollman.map.rpt

实现FPGA的加密程序

+------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                           ;
+----------------------------------+-----------------+------------------------+------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path       ;
+----------------------------------+-----------------+------------------------+------------------------------------+
; gollman.v                        ; yes             ; User Verilog HDL File  ; E:/FPGA/FPGA加密/gollman/gollman.v ;
+----------------------------------+-----------------+------------------------+------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 32    ;
;                                             ;       ;
; Total combinational functions               ; 26    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 4     ;
;     -- 3 input functions                    ; 2     ;
;     -- <=2 input functions                  ; 20    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 26    ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 32    ;
;     -- Dedicated logic registers            ; 32    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 9     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 32    ;
; Total fan-out                               ; 171   ;
; Average fan-out                             ; 2.55  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |gollman                   ; 26 (26)           ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 9    ; 0            ; |gollman            ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 32    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 28    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 26    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------+
; Inverted Register Statistics                      ;
+-----------------------------------------+---------+
; Inverted Register                       ; Fan out ;
+-----------------------------------------+---------+
; donei                                   ; 2       ;
; srd[1]                                  ; 1       ;
; sra[1]                                  ; 3       ;
; src[1]                                  ; 2       ;
; srd[3]                                  ; 2       ;
; sra[3]                                  ; 1       ;
; srb[3]                                  ; 2       ;
; src[0]                                  ; 1       ;
; srd[4]                                  ; 1       ;
; sra[4]                                  ; 1       ;
; srb[0]                                  ; 1       ;
; srd[5]                                  ; 2       ;
; sra[6]                                  ; 2       ;
; srd[7]                                  ; 1       ;
; srd[9]                                  ; 1       ;
; srd[10]                                 ; 1       ;
; Total number of inverted registers = 16 ;         ;
+-----------------------------------------+---------+


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |gollman ;
+----------------+--------------+-----------------------------------------+
; Parameter Name ; Value        ; Type                                    ;
+----------------+--------------+-----------------------------------------+
; keya           ; 1011011      ; Unsigned Binary                         ;
; keyb           ; 1001         ; Unsigned Binary                         ;
; keyc           ; 011          ; Unsigned Binary                         ;
; keyd           ; 011010111010 ; Unsigned Binary                         ;
+----------------+--------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Aug 15 09:45:28 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gollman -c gollman
Info: Found 1 design units, including 1 entities, in source file gollman.v
    Info: Found entity 1: gollman
Info: Elaborating entity "gollman" for the top level hierarchy
Critical Warning (10237): Verilog HDL warning at gollman.v(143): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead
Critical Warning (10237): Verilog HDL warning at gollman.v(169): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 44 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 6 output pins
    Info: Implemented 35 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 148 megabytes of memory during processing
    Info: Processing ended: Fri Aug 15 09:45:30 2008
    Info: Elapsed time: 00:00:02