fpga_pro.map.rpt

实现FPGA的加密程序

; gollman:inst|srd[9]                     ; 1       ;
; gollman:inst|srd[10]                    ; 1       ;
; Total number of inverted registers = 16 ;         ;
+-----------------------------------------+---------+


+-----------------------------------------------------------------------------+
; Source assignments for lpm_counter0:inst6|lpm_counter:lpm_counter_component ;
+---------------------------+-------+------+----------------------------------+
; Assignment                ; Value ; From ; To                               ;
+---------------------------+-------+------+----------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                ;
+---------------------------+-------+------+----------------------------------+


+-----------------------------------------------------------+
; Parameter Settings for User Entity Instance: gollman:inst ;
+----------------+--------------+---------------------------+
; Parameter Name ; Value        ; Type                      ;
+----------------+--------------+---------------------------+
; keya           ; 1011011      ; Unsigned Binary           ;
; keyb           ; 1001         ; Unsigned Binary           ;
; keyc           ; 011          ; Unsigned Binary           ;
; keyd           ; 011010111010 ; Unsigned Binary           ;
+----------------+--------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: gollstt:inst1 ;
+----------------+-------+-----------------------------------+
; Parameter Name ; Value ; Type                              ;
+----------------+-------+-----------------------------------+
; st0            ; 0001  ; Unsigned Binary                   ;
; st1            ; 0010  ; Unsigned Binary                   ;
; st2            ; 0100  ; Unsigned Binary                   ;
; st3            ; 1000  ; Unsigned Binary                   ;
+----------------+-------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_counter0:inst6|lpm_counter:lpm_counter_component ;
+------------------------+-------------+------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                       ;
+------------------------+-------------+------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                             ;
; LPM_WIDTH              ; 8           ; Signed Integer                                             ;
; LPM_DIRECTION          ; UP          ; Untyped                                                    ;
; LPM_MODULUS            ; 0           ; Untyped                                                    ;
; LPM_AVALUE             ; UNUSED      ; Untyped                                                    ;
; LPM_SVALUE             ; UNUSED      ; Untyped                                                    ;
; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                    ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                    ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                    ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                         ;
; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                         ;
; CARRY_CNT_EN           ; SMART       ; Untyped                                                    ;
; LABWIDE_SCLR           ; ON          ; Untyped                                                    ;
; USE_NEW_VERSION        ; TRUE        ; Untyped                                                    ;
; CBXI_PARAMETER         ; cntr_ihi    ; Untyped                                                    ;
+------------------------+-------------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Aug 15 10:16:47 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FPGA_pro -c FPGA_pro
Info: Found 1 design units, including 1 entities, in source file FPGA_pro.bdf
    Info: Found entity 1: FPGA_pro
Info: Found 1 design units, including 1 entities, in source file gollman.v
    Info: Found entity 1: gollman
Info: Found 1 design units, including 1 entities, in source file gollstt.v
    Info: Found entity 1: gollstt
Info: Elaborating entity "FPGA_pro" for the top level hierarchy
Info: Elaborating entity "gollman" for hierarchy "gollman:inst"
Critical Warning (10237): Verilog HDL warning at gollman.v(144): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead
Critical Warning (10237): Verilog HDL warning at gollman.v(170): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead
Info: Elaborating entity "gollstt" for hierarchy "gollstt:inst1"
Warning: Using design file lpm_counter0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_counter0
Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst6"
Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst6|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "lpm_counter0:inst6|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_ihi.tdf
    Info: Found entity 1: cntr_ihi
Info: Elaborating entity "cntr_ihi" for hierarchy "lpm_counter0:inst6|lpm_counter:lpm_counter_component|cntr_ihi:auto_generated"
Info: State machine "|FPGA_pro|gollstt:inst1|pres_s" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|FPGA_pro|gollstt:inst1|pres_s"
Info: Encoding result for state machine "|FPGA_pro|gollstt:inst1|pres_s"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "gollstt:inst1|pres_s.st3"
        Info: Encoded state bit "gollstt:inst1|pres_s.st2"
        Info: Encoded state bit "gollstt:inst1|pres_s.st1"
        Info: Encoded state bit "gollstt:inst1|pres_s.st0"
    Info: State "|FPGA_pro|gollstt:inst1|pres_s.st0" uses code string "0000"
    Info: State "|FPGA_pro|gollstt:inst1|pres_s.st1" uses code string "0011"
    Info: State "|FPGA_pro|gollstt:inst1|pres_s.st2" uses code string "0101"
    Info: State "|FPGA_pro|gollstt:inst1|pres_s.st3" uses code string "1001"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 58 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 4 output pins
    Info: Implemented 50 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 152 megabytes of memory during processing
    Info: Processing ended: Fri Aug 15 10:16:51 2008
    Info: Elapsed time: 00:00:04