gollstt.v

实现FPGA的加密程序

/*
Gollstt.vhd
-- State machine to implement handshake between two unsynchronized pseudo-random
-- sequence generators. Using this handshake technique, one of the sequence generators
-- can be implemented in h/w and one in s/w.

*/

module gollstt( clk,reset,done1,done2,ena,cmp_ena );

parameter	st0 = 4'b0001;
parameter	st1 = 4'b0010;	
parameter	st2 = 4'b0100;
parameter	st3 = 4'b1000;

input clk;
input reset;
input done1;
input done2;

output ena;
output cmp_ena;

reg ena;
reg cmp_ena;

reg [3:0] pres_s,next_s;

//This state machine's outputs depend only on state variable, regardless of
//implementation, therefore this is a Moore State Machine
//This process simply resets the state m/c and
always@( posedge clk or negedge reset )
	begin
		if( !reset )
			pres_s <= st0;
		else
			pres_s <= next_s;
	end

//This is the combinatorial process
always@( done1 or done2 or pres_s )
	begin
		case( pres_s )
			st0 : next_s <= st1;
			st1 : 
				if( done1 == 1'b1 | done2 == 1'b1 )
					next_s <= st1;
				else
					next_s <= st2;	//when both done1 and done2 are 0  
			st2 : 
				if( done1 == 1'b0 | done2 == 1'b0 )
					next_s <= st2;	//when any one of done1 or done2 are 0, stay st2 status
				else
					next_s <= st3;	//when both done1 and done2 are 1,turn to st3 status
			st3 : next_s <= st1;	//one time compare has finished
			default : next_s <= st0;
		endcase
	end
//This process assigns the outputs
always@( pres_s )
	begin
		if( pres_s == st1 )
			ena <= 1'b1;	//enable GOLLMAN module to generat random data
		else
			ena <= 1'b0;	//disable GOLLMAN module
		if( pres_s == st3 )
			cmp_ena <= 1'b1;	//Comparator enable during state 3
		else
			cmp_ena <= 1'b0;	//
	end

endmodule