fpga_pro.tan.rpt

实现FPGA的加密程序

+-------------------------------------------------------------------------------------+
; tco                                                                                 ;
+-------+--------------+------------+--------------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From                     ; To      ; From Clock ;
+-------+--------------+------------+--------------------------+---------+------------+
; N/A   ; None         ; 7.944 ns   ; gollstt:inst1|pres_s.st3 ; cmp_ena ; clk        ;
; N/A   ; None         ; 7.914 ns   ; gollman:inst|srd[0]      ; data2   ; clk        ;
; N/A   ; None         ; 7.331 ns   ; gollstt:inst1|pres_s.st1 ; ena     ; clk        ;
; N/A   ; None         ; 7.321 ns   ; inst5                    ; secure  ; clk        ;
+-------+--------------+------------+--------------------------+---------+------------+


+---------------------------------------------------------------------------------------+
; th                                                                                    ;
+---------------+-------------+-----------+-------+--------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To                       ; To Clock ;
+---------------+-------------+-----------+-------+--------------------------+----------+
; N/A           ; None        ; -0.724 ns ; reset ; gollman:inst|last_ena    ; clk      ;
; N/A           ; None        ; -0.724 ns ; reset ; gollman:inst|enad        ; clk      ;
; N/A           ; None        ; -0.724 ns ; reset ; gollman:inst|enac        ; clk      ;
; N/A           ; None        ; -0.724 ns ; reset ; gollman:inst|enab        ; clk      ;
; N/A           ; None        ; -4.131 ns ; data  ; inst5                    ; clk      ;
; N/A           ; None        ; -4.437 ns ; done  ; gollstt:inst1|pres_s.st2 ; clk      ;
; N/A           ; None        ; -4.438 ns ; done  ; gollstt:inst1|pres_s.st3 ; clk      ;
; N/A           ; None        ; -4.712 ns ; done  ; gollstt:inst1|pres_s.st1 ; clk      ;
+---------------+-------------+-----------+-------+--------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Aug 15 10:17:05 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FPGA_pro -c FPGA_pro --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 290.19 MHz between source register "gollman:inst|iena" and destination register "gollman:inst|src[1]" (period= 3.446 ns)
    Info: + Longest register to register delay is 3.165 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y12_N17; Fanout = 12; REG Node = 'gollman:inst|iena'
        Info: 2: + IC(0.477 ns) + CELL(0.366 ns) = 0.843 ns; Loc. = LCCOMB_X10_Y12_N28; Fanout = 2; COMB Node = 'gollman:inst|always3~0'
        Info: 3: + IC(1.467 ns) + CELL(0.855 ns) = 3.165 ns; Loc. = LCFF_X10_Y4_N5; Fanout = 2; REG Node = 'gollman:inst|src[1]'
        Info: Total cell delay = 1.221 ns ( 38.58 % )
        Info: Total interconnect delay = 1.944 ns ( 61.42 % )
    Info: - Smallest clock skew is -0.017 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.785 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 45; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.836 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X10_Y4_N5; Fanout = 2; REG Node = 'gollman:inst|src[1]'
            Info: Total cell delay = 1.806 ns ( 64.85 % )
            Info: Total interconnect delay = 0.979 ns ( 35.15 % )
        Info: - Longest clock path from clock "clk" to source register is 2.802 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 45; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.853 ns) + CELL(0.666 ns) = 2.802 ns; Loc. = LCFF_X10_Y12_N17; Fanout = 12; REG Node = 'gollman:inst|iena'
            Info: Total cell delay = 1.806 ns ( 64.45 % )
            Info: Total interconnect delay = 0.996 ns ( 35.55 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "gollstt:inst1|pres_s