📄 init.s
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;**************************************************************************
; *
; PROJECT : ARM port for UCOS-II *
; *
; MODULE : INIT.s *
; *
; AUTHOR : Michael Anburaj *
; URL : http://geocities.com/michaelanburaj/ *
; EMAIL: michaelanburaj@hotmail.com *
; *
; PROCESSOR : S3c2410x (32 bit ARM920T RISC core from Samsung) *
; *
; IDE : SDT 2.51 & ADS 1.2 *
; *
; DESCRIPTION : *
; S3c2410x processor Start up assembly code file. *
; *
;*************************************************************************/
GBLL PLL_ON_START
PLL_ON_START SETL {TRUE}
GBLL ENDIAN_CHANGE
ENDIAN_CHANGE SETL {FALSE}
GBLA ENTRY_BUS_WIDTH
ENTRY_BUS_WIDTH SETA 16
;BUSWIDTH = 16,32
GBLA BUSWIDTH ; max. bus width for the GPIO configuration
BUSWIDTH SETA 32
GBLA FCLK
FCLK SETA 50000000
[ FCLK = 20000000
M_MDIV EQU 0x20 ;Fin=12.0MHz Fout=20.0MHz
M_PDIV EQU 0x4
M_SDIV EQU 0x2
]
[ FCLK = 30000000
M_MDIV EQU 0x34 ;Fin=12.0MHz Fout=30.0MHz
M_PDIV EQU 0x4
M_SDIV EQU 0x2
]
[ FCLK = 50000000
M_MDIV EQU 0x5c ;Fin=12.0MHz Fout=50.0MHz
M_PDIV EQU 0x4
M_SDIV EQU 0x2
]
[ FCLK = 60000000
M_MDIV EQU 0x70 ;Fin=12.0MHz Fout=60.0MHz
M_PDIV EQU 0x4
M_SDIV EQU 0x2
]
[ FCLK = 70000000
M_MDIV EQU 0x84 ;Fin=12.0MHz Fout=70.0MHz
M_PDIV EQU 0x4
M_SDIV EQU 0x2
]
[ FCLK = 75000000
M_MDIV EQU 0x8e ;Fin=12.0MHz Fout=75.0MHz
M_PDIV EQU 0x4
M_SDIV EQU 0x2
]
[ FCLK = 176000000
M_MDIV EQU 80 ; Fin=12.0MHz Fout=176.0MHz
M_PDIV EQU 1
M_SDIV EQU 1
]
[ FCLK = 180000000
M_MDIV EQU 82 ; Fin=12.0MHz Fout=180.0MHz
M_PDIV EQU 1
M_SDIV EQU 1
]
[ FCLK = 184000000
M_MDIV EQU 84 ; Fin=12.0MHz Fout=184.0MHz
M_PDIV EQU 1
M_SDIV EQU 1
]
[ FCLK = 192000000
M_MDIV EQU 88 ; Fin=12.0MHz Fout=192.0MHz
M_PDIV EQU 1
M_SDIV EQU 1
]
SRAM_SADDR EQU 0x40000000 ; SRAM starting address
SRAM_SIZE EQU 4*1024 ; 4K internal SRAM
SDRAM_SADDR EQU 0x30000000 ; SDRAM starting address
SDRAM_SIZE EQU 64*1024*1024 ; 64M SDRAM
ISR_BADDR EQU 0x33ffff00 ; plus 0x20 is the RW base address -linker setting
SRAM_EADDR EQU SRAM_SADDR+SRAM_SIZE-1 ; SRAM end address
SDRAM_EADDR EQU SDRAM_SADDR+SDRAM_SIZE-1 ; SDRAM end address
MMUTT_SIZE EQU 16*1024 ; It has to be in multiples of 16K
MMUTT_SADDR EQU SDRAM_SADDR
MMUTT_EADDR EQU MMUTT_SADDR+MMUTT_SIZE
_SVC_STKSIZE EQU 1024*20
_UND_STKSIZE EQU 256
_ABT_STKSIZE EQU 256
_IRQ_STKSIZE EQU 1024*1
_FIQ_STKSIZE EQU 256
STK_SIZE EQU _SVC_STKSIZE+_UND_STKSIZE+_ABT_STKSIZE+_IRQ_STKSIZE+_FIQ_STKSIZE
STK_SADDR EQU ISR_BADDR-STK_SIZE
; Register definition
GET S3c2410x.a
GET memcfg.a
BIT_SELFREFRESH EQU (1<<22)
; Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=$HandleLabel
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
MEND
; Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
GBLL THUMBCODE
[ {CONFIG} = 16
THUMBCODE SETL {TRUE}
CODE32
|
THUMBCODE SETL {FALSE}
]
MACRO
MOV_PC_LR
[ THUMBCODE
bx lr
|
mov pc,lr
]
MEND
MACRO
MOVEQ_PC_LR
[ THUMBCODE
bxeq lr
|
moveq pc,lr
]
MEND
AREA |Init|, CODE, READONLY
ENTRY
ASSERT :DEF:ENDIAN_CHANGE
[ ENDIAN_CHANGE
ASSERT :DEF:ENTRY_BUS_WIDTH
[ ENTRY_BUS_WIDTH=32
b ChangeBigEndian ; DCD 0xea000007
]
[ ENTRY_BUS_WIDTH=16
andeq r14,r7,r0,lsl #20 ; DCD 0x0007ea00
]
[ ENTRY_BUS_WIDTH=8
streq r0,[r0,-r10,ror #1] ; DCD 0x070000ea
]
|
b ResetHandler
]
b HandlerUndef ; handlerUndef
b HandlerSWI ; SWI interrupt handler
b HandlerPabort ; handlerPAbort
b HandlerDabort ; handlerDAbort
b . ; handlerReserved
b HandlerIRQ ; handlerIRQ
b HandlerFIQ ; handlerFIQ
; @0x20
b EnterPWDN
; @0x24
ChangeBigEndian
[ ENTRY_BUS_WIDTH=32
DCD 0xee110f10 ; 0xee110f10 => mrc p15,0,r0,c1,c0,0
DCD 0xe3800080 ; 0xe3800080 => orr r0,r0,#0x80; //Big-endian
DCD 0xee010f10 ; 0xee010f10 => mcr p15,0,r0,c1,c0,0
]
[ ENTRY_BUS_WIDTH=16
DCD 0x0f10ee11
DCD 0x0080e380
DCD 0x0f10ee01
]
[ ENTRY_BUS_WIDTH=8
DCD 0x100f11ee
DCD 0x800080e3
DCD 0x100f01ee
]
DCD 0xffffffff ; swinv 0xffffff is similar with NOP and run well in both endian mode.
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
b ResetHandler
; Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on.
; 5. The location of the following code may have not to be changed.
; void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ; r2=rCLKCON
tst r0,#0x8 ; POWER_OFF mode?
bne ENTER_POWER_OFF
ENTER_STOP
ldr r0,=REFRESH
ldr r3,[r0] ; r3=rREFRESH
mov r1, r3
orr r1, r1, #BIT_SELFREFRESH
str r1, [r0] ; Enable SDRAM self-refresh
mov r1,#16 ; wait until self-refresh is issued. may not be needed.
0 subs r1,r1,#1
bne %B0
ldr r0,=CLKCON ; enter STOP mode.
str r2,[r0]
mov r1,#32
0 subs r1,r1,#1 ; 1) wait until the STOP mode is in effect.
bne %B0 ; 2) Or wait here until the CPU&Peripherals will be turned-off
; Entering POWER_OFF mode, only the reset by wake-up is available.
ldr r0,=REFRESH ; exit from SDRAM self refresh mode.
str r3,[r0]
MOV_PC_LR
ENTER_POWER_OFF
; NOTE.
; 1) rGSTATUS3 should have the return address after wake-up from POWER_OFF mode.
ldr r0,=REFRESH
ldr r1,[r0] ; r1=rREFRESH
orr r1, r1, #BIT_SELFREFRESH
str r1, [r0] ; Enable SDRAM self-refresh
mov r1,#16 ; Wait until self-refresh is issued,which may not be needed.
0 subs r1,r1,#1
bne %B0
ldr r1,=MISCCR
ldr r0,[r1]
orr r0,r0,#(7<<17) ; Make sure that SCLK0:SCLK->0, SCLK1:SCLK->0, SCKE=L during boot-up
str r0,[r1]
ldr r0,=CLKCON
str r2,[r0]
b . ; CPU will die here.
WAKEUP_POWER_OFF
; Release SCLKn after wake-up from the POWER_OFF mode.
ldr r1,=MISCCR
ldr r0,[r1]
bic r0,r0,#(7<<17) ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
str r0,[r1]
; Set memory control registers
ldr r0,=SMRDATA
ldr r1,=BWSCON ; BWSCON Address
add r2, r0, #52 ; End address of SMRDATA
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0
mov r1,#256
0 subs r1,r1,#1 ; 1) wait until the SelfRefresh is released.
bne %B0
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