uart.qsf

全面模仿AVR的UART功能

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		uart_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.

set_location_assignment PIN_38 -to ad[0]
set_location_assignment PIN_39 -to ad[1]
set_location_assignment PIN_40 -to ad[2]
set_location_assignment PIN_41 -to ad[3]
set_location_assignment PIN_42 -to ad[4]
set_location_assignment PIN_47 -to ad[5]
set_location_assignment PIN_48 -to ad[6]
set_location_assignment PIN_49 -to ad[7]
set_location_assignment PIN_51 -to addr[7]
set_location_assignment PIN_52 -to addr[6]
set_location_assignment PIN_53 -to addr[5]
set_location_assignment PIN_54 -to addr[4]
set_location_assignment PIN_55 -to addr[3]
set_location_assignment PIN_56 -to addr[2]
set_location_assignment PIN_57 -to addr[1]
set_location_assignment PIN_58 -to addr[0]
set_location_assignment PIN_50 -to ale
set_location_assignment PIN_16 -to clk
set_location_assignment PIN_59 -to rd_n
set_location_assignment PIN_60 -to wr_n
set_location_assignment PIN_93 -to rst_n
set_location_assignment PIN_32 -to rxd
set_location_assignment PIN_33 -to txd
set_location_assignment PIN_83 -to uart_clk

set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:54:20  MARCH 19, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -entity uart -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -entity uart -section_id "Root Region"
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_location_assignment PIN_37 -to int_o
set_global_assignment -name VERILOG_FILE src/divider.v
set_global_assignment -name VERILOG_FILE src/ebi.v
set_global_assignment -name VERILOG_FILE src/rxd.v
set_global_assignment -name VERILOG_FILE src/top.v
set_global_assignment -name VERILOG_FILE src/txd.v
set_global_assignment -name VERILOG_FILE src/uart.v
set_global_assignment -name SAFE_STATE_MACHINE ON