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<H2>2.6 Datapath Logic Cells</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=88254"></A>Suppose we wish to
build an <SPAN CLASS="EmphasisPrefix"> n</SPAN> -bit adder (that adds two
<SPAN CLASS="EmphasisPrefix"> n</SPAN> -bit numbers) and to exploit the
regularity of this function in the layout. We can do so using a datapath
structure.</P>
<P><P CLASS="Body"><A NAME="pgfId=142353"></A>The following two functions,
SUM and COUT, implement the sum and carry out for a <B>full adder</B> (<B>
FA</B> ) with two data inputs (A, B) and a carry in, CIN:</P>
<P><P CLASS="EqnNmbrdAlign"><A NAME="pgfId=86973"></A> SUM<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>A<SPAN CLASS="White"> </SPAN><SPAN CLASS="Symbol">
</SPAN> <SPAN CLASS="White"> </SPAN>B<SPAN CLASS="Symbol">
</SPAN> <SPAN CLASS="White"> </SPAN>CIN<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>SUM(A,
B, CIN)<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>PARITY(A,
B, CIN),(2.38)</P>
<P><P CLASS="EqnNmbrdAlign"><A NAME="pgfId=99870"></A> COUT<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>A<SPAN CLASS="White"> </SPAN>·<SPAN CLASS="White"> </SPAN>B<SPAN CLASS="White"> </SPAN>+<SPAN CLASS="White"> </SPAN>A<SPAN CLASS="White"> </SPAN>·<SPAN CLASS="White"> </SPAN>CIN<SPAN CLASS="White"> </SPAN>+<SPAN CLASS="White"> </SPAN>B<SPAN CLASS="White"> </SPAN>·<SPAN CLASS="White"> </SPAN>CIN<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>MAJ(A,
B, CIN).(2.39)</P>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=99872"></A>The sum uses the <B>parity
function</B> ('1' if there are an odd numbers of '1's in the inputs). The
carry out, COUT, uses the 2-of-3 <B>majority function</B> ('1' if the majority
of the inputs are '1'). We can combine these two functions in a single FA
logic cell, ADD(A[<SPAN CLASS="EquationVariables"> i</SPAN> ], B[<SPAN CLASS="EquationVariables">
i</SPAN> ], CIN, S[<SPAN CLASS="EquationVariables"> i</SPAN> ], COUT), shown
in Figure 2.20(a), where</P>
<P><P CLASS="EqnNmbrdAlign"><A NAME="pgfId=87175"></A> S[<SPAN CLASS="EquationVariables">
i</SPAN> <SPAN CLASS="White"> </SPAN>]<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>SUM(A[<SPAN CLASS="EquationVariables">
i</SPAN> ], B[<SPAN CLASS="EquationVariables"> i</SPAN> ], CIN),(2.40)</P>
<P><P CLASS="EqnNmbrdAlign"><A NAME="pgfId=87176"></A> COUT<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>MAJ(A[<SPAN CLASS="EquationVariables">
i</SPAN> ], B[<SPAN CLASS="EquationVariables"> i</SPAN> ], CIN).(2.41)</P>
<P><P CLASS="Body"><A NAME="pgfId=105349"></A>Now we can build a 4-bit <B>ripple-carry
adder</B> (<B> RCA</B> ) by connecting four of these ADD cells together
as shown in Figure 2.20(b). The <SPAN CLASS="EquationVariables"> i<SPAN CLASS="White"> </SPAN></SPAN>
th ADD cell is arranged with the following: two bus inputs A[<SPAN CLASS="EquationVariables">
i</SPAN> ], B[<SPAN CLASS="EquationVariables"> i</SPAN> ]; one bus output
S[<SPAN CLASS="EquationVariables"> i</SPAN> ]; an input, CIN, that is the
carry in from stage (<SPAN CLASS="EquationVariables"> i</SPAN> <SPAN CLASS="White"> </SPAN>–<SPAN CLASS="White"> </SPAN>1)
below and is also passed up to the cell above as an output; and an output,
COUT, that is the carry out to stage (<SPAN CLASS="EquationVariables"> i</SPAN>
<SPAN CLASS="White"> </SPAN>+<SPAN CLASS="White"> </SPAN>1)
above. In the 4-bit adder shown in Figure 2.20(b) we connect the carry
input, CIN[0], to VSS and use COUT[3] and COUT[2] to indicate arithmetic
overflow (in Section 2.6.1 we shall see why we may need both signals).
Notice that we build the ADD cell so that COUT[2] is available at the top
of the datapath when we need it.</P>
<P><P CLASS="Body"><A NAME="pgfId=87115"></A>Figure 2.20(c) shows a
layout of the ADD cell. The A inputs, B inputs, and S outputs all use m1
interconnect running in the horizontal directionwe call these <B>data</B>
signals. Other signals can enter or exit from the top or bottom and run
vertically across the datapath in m2we call these <B>control</B> signals.
We can also use m1 for control and m2 for data, but we normally do not mix
these approaches in the same structure. Control signals are typically clocks
and other signals common to elements. For example, in Figure 2.20(c)
the carry signals, CIN and COUT, run vertically in m2 between cells. To
build a 4-bit adder we stack four ADD cells creating the array structure
shown in Figure 2.20(d). In this case the A and B data bus inputs enter
from the left and bus S, the sum, exits at the right, but we can connect
A, B, and S to either side if we want.</P>
<P><P CLASS="Body"><A NAME="pgfId=87469"></A>The layout of buswide logic
that operates on data signals in this fashion is called a <B>datapath</B>
. The module ADD is a <B>datapath cell</B> or <B>datapath element</B> .
Just as we do for standard cells we make all the datapath cells in a library
the same height so we can abut other datapath cells on either side of the
adder to create a more complex datapath. When people talk about a datapath
they always assume that it is oriented so that increasing the size in bits
makes the datapath grow in height, upwards in the vertical direction, and
adding different datapath elements to increase the function makes the datapath
grow in width, in the horizontal directionbut we can rotate and position
a completed datapath in any direction we want on a chip.</P>
<P><TABLE BORDER="0" CELLSPACING="2" CELLPADDING="0">
<TR>
<TD><P><P CLASS="TableFigure"><A NAME="pgfId=87029"></A> </P>
<P><IMG SRC="CH02-62.gif" WIDTH="446" HEIGHT="176" NATURALSIZEFLAG="3"
ALIGN="BOTTOM"></TD></TR>
<TR>
<TD><P CLASS="TableFigureTitle"><A NAME="pgfId=87032"></A>FIGURE 2.20 A
datapath adder. (a) A full-adder (FA) cell with inputs (A and B), a
carry in, CIN, sum output, S, and carry out, COUT. (b) A 4-bit adder.
(c) The layout, using two-level metal, with data in m1 and control
in m2. In this example the wiring is completed outside the cell; it is also
possible to design the datapath cells to contain the wiring. Using three
levels of metal, it is possible to wire over the top of the datapath cells.
(d) The datapath layout.</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=85578"></A>What is the difference between
using a datapath, standard cells, or gate arrays? Cells are placed together
in rows on a CBIC or an MGA, but there is no generally no regularity to
the arrangement of the cells within the rowswe let software arrange the
cells and complete the interconnect. Datapath layout automatically takes
care of most of the interconnect between the cells with the following advantages:</P>
<UL>
<LI><A NAME="pgfId=88273"></A>Regular layout produces predictable and equal
delay for each bit.
<LI><A NAME="pgfId=88274"></A>Interconnect between cells can be built into
each cell.
</UL>
<P><P CLASS="Body"><A NAME="pgfId=88276"></A>There are some disadvantages
of using a datapath:</P>
<UL>
<LI><A NAME="pgfId=88277"></A>The overhead (buffering and routing the control
signals, for example) can make a narrow (small number of bits) datapath
larger and slower than a standard-cell (or even gate-array) implementation.
<LI><A NAME="pgfId=88278"></A>Datapath cells have to be predesigned (otherwise
we are using full-custom design) for use in a wide range of datapath sizes.
Datapath cell design can be harder than designing gate-array macros or
standard cells.
<LI><A NAME="pgfId=88279"></A>Software to assemble a datapath is more complex
and not as widely used as software for assembling standard cells or gate
arrays.
</UL>
<P><P CLASS="Body"><A NAME="pgfId=142366"></A>There are some newer standard-cell
and gate-array tools that can take advantage of regularity in a design and
position cells carefully. The problem is in finding the regularity if it
is not specified. Using a datapath is one way to specify regularity to ASIC
design tools.</P>
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