📄 ch02.4.htm
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To add transistors in parallel, make all the lengths 1 and add the widths.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=104867">
</A>
To add transistors in series, make all the widths 1 and add the lengths.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=201847">
</A>
We have to be careful to keep W and L reasonable. For example, a 3/1 in series with a 2/1 is equivalent to a 1/((1/3) + (1/2)) or 1/0.83. Since we cannot make a device 2 <SPAN CLASS="Symbol">
l</SPAN>
wide and 1.66 <SPAN CLASS="Symbol">
l</SPAN>
long, a 1/0.83 is more naturally written as 3/2.5. We like to keep both W and L as integer multiples of 0.5 (equivalent to making W and L integer multiples of <SPAN CLASS="Symbol">
l</SPAN>
), but W and L must be greater than 1. </P>
<P CLASS="Body">
<A NAME="pgfId=201825">
</A>
In Figure 2.13(c) the transistors in the AOI221 cell are sized so that any string through the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel stack has a drive strength equivalent to a 2/1 <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor (we choose the worst case, if more than one transistor in parallel is conducting then the drive strength will be higher). The <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel stack is sized so that it has a drive strength of a 1/1 <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor. The ratio in this library is thus 2.</P>
<P CLASS="Body">
<A NAME="pgfId=39864">
</A>
If we were to use four drive strengths for each of the AOI family of cells shown in Table 2.10, we would have a total of 224 combinational library cells—just for the AOI family. The synthesis tools can handle this number of cells, but we may not be able to design this many cells in a reasonable amount of time. Section 3.3, “Logical Effort,” will help us choose the most logically efficient cells.</P>
</DIV>
<DIV>
<H3 CLASS="Heading2">
<A NAME="pgfId=8374">
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2.4.3 Transmission Gates</H3>
<P CLASS="BodyAfterHead">
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Figure 2.14(a) and (b) shows a CMOS <SPAN CLASS="Definition">
transmission gate</SPAN>
(<SPAN CLASS="Definition">
TG</SPAN>
, TX gate, pass gate, coupler). We connect a <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor (to transmit a strong '1') in parallel with an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor (to transmit a strong '0'). </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
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</A>
<IMG SRC="CH02-26.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=53975">
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FIGURE 2.14 CMOS transmission gate (TG). (a) An <SPAN CLASS="EmphasisPrefix">
n-</SPAN>
channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor in parallel form a TG. (b) A common symbol for a TG. (c) The charge-sharing problem.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=53981">
</A>
We can express the function of a TG as </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379271">
</A>
Z = TG(A, S) ,</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=379273">
</A>
(2.27)</P>
</TD>
</TR>
</TABLE>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=53612">
</A>
but this is ambiguous—if we write TG(X, Y), how do we know if X is connected to the gates or sources/drains of the TG? We shall always define TG(X, Y) when we use it. It is tempting to write TG(A, S) = A · S, but what is the value of Z when S ='0' in Figure 2.14(a), since Z is then left floating? A TG is a switch, not an AND logic cell.</P>
<P CLASS="Body">
<A NAME="pgfId=53699">
</A>
There is a potential problem if we use a TG as a switch connecting a node Z that has a large capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
BIG</SUB>
, to an input node A that has only a small capacitance <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
SMALL</SUB>
(see Figure 2.14c). If the initial voltage at A is <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
SMALL</SUB>
and the initial voltage at Z is <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
BIG</SUB>
, when we close the TG (by setting S = '1') the final voltage on both nodes A and Z is </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=379344">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379346">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379348">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
BIG</SUB>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
BIG</SUB>
+ <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
SMALL</SUB>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SMALL</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=379350">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=379352">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=379354">
</A>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
F</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379356">
</A>
=</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379358">
</A>
<SPAN CLASS="EquationVariables">
–––––––––––––––––––––––––</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=379360">
</A>
.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=379362">
</A>
(2.28)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=379364">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379366">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379368">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
BIG</SUB>
+ <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
SMALL</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=379370">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=379372">
</A>
</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=53705">
</A>
Imagine we want to drive a '0' onto node Z from node A. Suppose <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
BIG</SUB>
= 0.2 pF (about 10 standard loads in a 0.5 <SPAN CLASS="Symbol">
m</SPAN>
m process) and <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
SMALL</SUB>
= 0.02 pF, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
BIG</SUB>
= 0 V and <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
SMALL</SUB>
= 5 V; then </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=379505">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379507">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379509">
</A>
(0.2 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–12</SUP>
) (0) + (0.02 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–12</SUP>
) (5)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379511">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=379513">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=379515">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=379517">
</A>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
F</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379519">
</A>
=</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379521">
</A>
<SPAN CLASS="EquationVariables">
––––––––––––––––––––––––––––</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379523">
</A>
=</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=379525">
</A>
0.45 V .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=379527">
</A>
(2.29)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=379529">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379531">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379533">
</A>
(0.2 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–12</SUP>
) + (0.02 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–12</SUP>
) </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379535">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=379537">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=379539">
</A>
</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=53710">
</A>
This is not what we want at all, the “big” capacitor has forced node A to a voltage close to a '0'. This type of problem is known as <SPAN CLASS="Definition">
charge sharing</SPAN>
. We should make sure that either (1) node A is strong enough to overcome the big capacitor, or (2) insulate node A from node Z by including a <SPAN CLASS="Definition">
buffer</SPAN>
(an inverter, for example) between node A and node Z. We must not use charge to drive another logic cell—only a logic cell can drive a logic cell. </P>
<P CLASS="Body">
<A NAME="pgfId=201983">
</A>
If we omit one of the transistors in a TG (usually the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor) we have a <SPAN CLASS="Definition">
pass transistor</SPAN>
. There is a branch of full-custom VLSI design that uses pass-transistor logic. Much of this is based on relay-based logic, since a single transistor switch looks like a relay contact. There are many problems associated with pass-transistor logic related to charge sharing, reduced noise margins, and the difficulty of predicting delays. Though pass transistors may appear in an ASIC cell inside a library, they are not used by ASIC designers. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=201990">
</A>
<IMG SRC="CH02-27.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=201994">
</A>
FIGURE 2.15 The CMOS multiplexer (MUX). (a) A noninverting 2:1 MUX using transmission gates without buffering. (b) A symbol for a MUX (note how the inputs are labeled). (c) An IEEE standard symbol for a MUX. (d) A nonstandard, but very common, IEEE symbol for a MUX. (e) An inverting MUX with output buffer. (f) A noninverting buffered MUX.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=201997">
</A>
We can use two TGs to form a <SPAN CLASS="Definition">
multiplexer</SPAN>
(or multiplexor—people use both orthographies) as shown in Figure 2.15(a). We often shorten multiplexer to <SPAN CLASS="Definition">
MUX</SPAN>
. The MUX function for two data inputs, A and B, with a select signal S, is </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=379552">
</A>
Z = TG(A, S') + TG(B, S) .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
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