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<H1 CLASS="Heading1">
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2.4 Combinational Logic Cells</H1>
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The AND-OR-INVERT (AOI) and the OR-AND-INVERT (OAI) logic cells are particularly efficient in CMOS. Figure 2.12 shows an AOI221 and an OAI321 logic cell (the logic symbols in Figure 2.12 are not standards, but are widely used). All indices (the indices are the numbers after AOI or OAI) in the logic cell name greater than 1 correspond to the inputs to the first “level” or stage—the AND gate(s) in an AOI cell, for example. An index of '1' corresponds to a direct input to the second-stage cell. We write indices in descending order; so it is AOI221 and not AOI122 (but both are equivalent cells), and AOI32 not AOI23. If we have more than one direct input to the second stage we repeat the '1'; thus an AOI211 cell performs the function Z = (A.B + C + D)'. A three-input NAND cell is an OAI111, but calling it that would be very confusing. These rules are not standard, but form a convention that we shall adopt and one that is widely used in the ASIC industry.</P>
<P CLASS="Body">
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There are many ways to represent the logical operator, AND. I shall use the <SPAN CLASS="Definition">
middle dot</SPAN>
and write A · B (rather than AB, A.B, or A <SPAN CLASS="Symbol">
∧</SPAN>
B); occasionally I may use AND(A, B). Similarly I shall write A + B as well as OR(A, B). I shall use an apostrophe like this, A', to denote the complement of A rather than <SPAN CLASS="Overline">
A</SPAN>
since sometimes it is difficult or inappropriate to use an overbar (<SPAN CLASS="Emphasis">
vinculum</SPAN>
) or diacritical mark (macron). It is possible to misinterpret AB' as A<SPAN CLASS="Overline">
B</SPAN>
rather than <SPAN CLASS="Overline">
AB</SPAN>
(but the former alternative would be A · B' in my convention). I shall be careful in these situations. </P>
<TABLE>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigTitleSide">
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FIGURE 2.12 Naming and numbering complex CMOS combinational cells. (a) An AND-OR-INVERT cell, an AOI221. (b) An OR-AND-INVERT cell, an OAI321. Numbering is always in descending order.</P>
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</TABLE>
<P CLASS="Body">
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We can express the function of the AOI221 cell in Figure 2.12(a) as </P>
<TABLE>
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<P CLASS="TableEqnCenter">
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Z = (A · B + C · D + E)' .</P>
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<P CLASS="TableEqnNumber">
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(2.25)</P>
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<P CLASS="BodyAfterHead">
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We can also write this equation unambiguously as Z = OAI221(A, B, C, D, E), just as we might write X = NAND (I, J, K) to describe the logic function X = (I · J · K)'. </P>
<P CLASS="Body">
<A NAME="pgfId=379177">
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This notation is useful because, for example, if we write OAI321(P, Q, R, S, T, U) we immediately know that U (the sixth input) is the (only) direct input connected to the second stage. Sometimes we need to refer to particular inputs without listing them all. We can adopt another convention that letters of the input names change with the index position. Now we can refer to input B2 of an AOI321 cell, for example, and know which input we are talking about without writing </P>
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Z = AOI321(A1, A2, A3, B1, B2, C) .</P>
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<P CLASS="TableEqnNumber">
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(2.26)</P>
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<P CLASS="Body">
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Table 2.10 shows the <SPAN CLASS="Definition">
AOI family</SPAN>
of logic cells with three indices (with branches in the family for AOI, OAI, AO, and OA cells). There are 5 types and 14 separate members of each branch of this family. There are thus 4 <SPAN CLASS="Symbol">
¥</SPAN>
14 = 56 cells of the type X<SPAN CLASS="EquationVariables">
abc</SPAN>
where X = {OAI, AOI, OA, AO} and each of the indexes <SPAN CLASS="EquationVariables">
a</SPAN>
, <SPAN CLASS="EquationVariables">
b</SPAN>
, and <SPAN CLASS="EquationVariables">
c</SPAN>
can range from 1 to 3. We form the AND-OR (AO) and OR-AND (OA) cells by adding an inverter to the output of an AOI or OAI cell. </P>
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<P CLASS="TableTitle">
<A NAME="pgfId=379187">
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TABLE 2.10 The AOI family of cells with three index numbers or less.</P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=379196">
</A>
<SPAN CLASS="TableHeads">
Cell type<A HREF="#pgfId=379195" CLASS="footnote">
1</A>
</SPAN>
</P>
</TD>
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<P CLASS="TableFirst">
<A NAME="pgfId=379198">
</A>
Cells </P>
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<P CLASS="TableFirst">
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<SPAN CLASS="TableHeads">
Number of unique cells</SPAN>
</P>
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<P CLASS="Table">
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Xa1 </P>
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<P CLASS="TableLeft">
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</A>
X21, X31</P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=379206">
</A>
2</P>
</TD>
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<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=379208">
</A>
Xa11 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=379210">
</A>
X211, X311</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=379212">
</A>
2</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=379214">
</A>
Xab</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=379216">
</A>
X22, X33, X32</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=379218">
</A>
3</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=379220">
</A>
Xab1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=379222">
</A>
X221, X331, X321</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=379224">
</A>
3</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=379226">
</A>
Xabc</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=379228">
</A>
X222, X333, X332, X322</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=379230">
</A>
4</P>
</TD>
</TR>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
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</A>
Total </P>
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<P CLASS="TableLeft">
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</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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</A>
14</P>
</TD>
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</TABLE>
<DIV>
<H3 CLASS="Heading2">
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2.4.1 Pushing Bubbles</H3>
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The AOI and OAI logic cells can be built using a single stage in CMOS using series–parallel networks of transistors called stacks. Figure 2.13 illustrates the procedure to build the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel stacks, using the AOI221 cell as an example.</P>
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<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
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</A>
</P>
<DIV>
<IMG SRC="CH02-25.gif">
</DIV>
</TD>
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<P CLASS="TableFigureTitle">
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FIGURE 2.13 Constructing a CMOS logic cell—an AOI221. (a) First build the dual icon by using de Morgan’s theorem to “push” inversion bubbles to the inputs. (b) Next build the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel stacks from series and parallel combinations of transistors. (c) Adjust transistor sizes so that the <SPAN CLASS="EmphasisPrefix">
n-</SPAN>
channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel stacks have equal strengths.</P>
</TD>
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</TABLE>
<P CLASS="Body">
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Here are the steps to construct any single-stage combinational CMOS logic cell:</P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=177812">
</A>
Draw a schematic icon with an inversion (bubble) on the last cell (the bubble-out schematic). Use <SPAN CLASS="Definition">
de Morgan’s theorems</SPAN>
—“A NAND is an OR with inverted inputs and a NOR is an AND with inverted inputs”—to push the output bubble back to the inputs (this the dual icon or bubble-in schematic).</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=44194">
</A>
Form the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel stack working from the inputs on the bubble-out schematic: OR translates to a parallel connection, AND translates to a series connection. If you have a bubble at an input, you need an inverter.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=44198">
</A>
Form the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel stack using the bubble-in schematic (ignore the inversions at the inputs—the bubbles on the gate terminals of the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistors take care of these). If you do not have a bubble at the input gate terminals, you need an inverter (these will be the same input gate terminals that had bubbles in the bubble-out schematic).</LI>
</OL>
<P CLASS="Body">
<A NAME="pgfId=44205">
</A>
The two stacks are <SPAN CLASS="Definition">
network duals</SPAN>
(they can be derived from each other by swapping series connections for parallel, and parallel for series connections). The <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel stack implements the strong '0's of the function and the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel stack provides the strong '1's. The final step is to adjust the drive strength of the logic cell by sizing the transistors. </P>
</DIV>
<DIV>
<H3 CLASS="Heading2">
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2.4.2 Drive Strength</H3>
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Normally we <SPAN CLASS="Definition">
ratio</SPAN>
the sizes of the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistors in an inverter so that both types of transistors have the same resistance, or <SPAN CLASS="Definition">
drive strength</SPAN>
. That is, we make <SPAN CLASS="Symbol">
b</SPAN>
<SUB CLASS="SubscriptVariable">
n</SUB>
= <SPAN CLASS="Symbol">
b</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
. At low dopant concentrations and low electric fields <SPAN CLASS="Symbol">
m</SPAN>
<SUB CLASS="SubscriptVariable">
n</SUB>
is about twice <SPAN CLASS="Symbol">
m</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
. To compensate we make the shape factor, W/L, of the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor in an inverter about twice that of the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor (we say the logic has a ratio of 2). Since the transistor lengths are normally equal to the minimum poly width for both types of transistors, the ratio of the transistor widths is also equal to 2. With the high dopant concentrations and high electric fields in submicron transistors the difference in mobilities is less—typically between 1 and 1.5.</P>
<P CLASS="Body">
<A NAME="pgfId=106453">
</A>
Logic cells in a library have a range of drive strengths. We normally call the minimum-size inverter a 1X inverter. The drive strength of a logic cell is often used as a suffix; thus a 1X inverter has a cell name such as INVX1 or INVD1. An inverter with transistors that are twice the size will be an INVX2. Drive strengths are normally scaled in a geometric ratio, so we have 1X, 2X, 4X, and (sometimes) 8X or even higher, drive-strength cells. We can size a logic cell using these basic rules: </P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=201809">
</A>
Any string of transistors connected between a power supply and the output in a cell with 1X drive should have the same resistance as the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor in a 1X inverter. </LI>
<LI CLASS="BulletList">
<A NAME="pgfId=104817">
</A>
A transistor with shape factor W<SUB CLASS="Subscript">
1</SUB>
/L<SUB CLASS="Subscript">
1</SUB>
has a resistance proportional to L<SUB CLASS="Subscript">
1</SUB>
/W<SUB CLASS="Subscript">
1 </SUB>
(so the larger W<SUB CLASS="Subscript">
1</SUB>
is, the smaller the resistance). </LI>
<LI CLASS="BulletList">
<A NAME="pgfId=201802">
</A>
Two transistors in parallel with shape factors W<SUB CLASS="Subscript">
1</SUB>
/L<SUB CLASS="Subscript">
1</SUB>
and W<SUB CLASS="Subscript">
2</SUB>
/L<SUB CLASS="Subscript">
2</SUB>
are equivalent to a single transistor (W<SUB CLASS="Subscript">
1</SUB>
/L<SUB CLASS="Subscript">
1</SUB>
+ W<SUB CLASS="Subscript">
2</SUB>
/L<SUB CLASS="Subscript">
2</SUB>
)/1. For example, a 2/1 in parallel with a 3/1 is a 5/1.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=104805">
</A>
Two transistors, with shape factors W<SUB CLASS="Subscript">
1</SUB>
/L<SUB CLASS="Subscript">
2</SUB>
and W<SUB CLASS="Subscript">
2</SUB>
/L<SUB CLASS="Subscript">
2</SUB>
, in series are equivalent to a single 1/(L<SUB CLASS="Subscript">
1</SUB>
/W<SUB CLASS="Subscript">
1</SUB>
+ L<SUB CLASS="Subscript">
2</SUB>
/W<SUB CLASS="Subscript">
2</SUB>
) transistor. </LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=201803">
</A>
For example, a transistor with shape factor 3/1 (we shall call this “a 3/1”) in series with another 3/1 is equivalent to a 1/((1/3) + (1/3)) or a 3/2. We can use the following method to calculate equivalent transistor sizes:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=104866">
</A>
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