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<H2>2.6.3 A Simple Example</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=196091"></A>How do we make and
use datapath elements? What does a design look like? We may use predesigned
cells from a library or build the elements ourselves from logic cells using
a schematic or a design language. Table 2.12 shows an 8-bit conditional-sum
adder intended for an FPGA. This Verilog implementation uses the same structure
as Figure 2.25, but the equations are collapsed to use four or five
variables. A basic logic cell in certain Xilinx FPGAs, for example, can
implement two equations of the same four variables or one equation with
five variables. The equations shown in Table 2.12 requires three levels
of FPGA logic cells (so, for example, if each FPGA logic cell has a 5<SPAN CLASS="White"> </SPAN>ns
delay, the 8-bit conditional-sum adder delay is 15<SPAN CLASS="White"> </SPAN>ns).</P>
<P><TABLE BORDER="0" CELLSPACING="2" CELLPADDING="0">
<TR>
<TD><P CLASS="TableTitle"><A NAME="pgfId=196299"></A>TABLE 2.12 An
8-bit conditional-sum adder (the notation is described in Figure 2.25).</TD></TR>
<TR>
<TD><SPAN CLASS="ComputerFirstLabelV"> <A NAME="pgfId=196303"></A><B>module</B>
m8bitCSum (C0, a, b, s, C8); // Verilog conditional-sum adder for an FPGA</SPAN>
<SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196304"></A><B>input</B> [7:0]
C0, a, b; <B>output</B> [7:0] s; <B>output</B> C8;</SPAN> <SPAN CLASS="ComputerLabelV">
<A NAME="pgfId=196305"></A><B>wire</B> A7,A6,A5,A4,A3,A2,A1,A0,B7,B6,B5,B4,B3,B2,B1,B0,S8,S7,S6,S5,S4,S3,S2,S1,S0;</SPAN>
<SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196306"></A><B>wire</B> C0,
C2, C4_2_0, C4_2_1, S5_4_0, S5_4_1, C6, C6_4_0, C6_4_1, C8;</SPAN> <SPAN CLASS="ComputerLabelV">
<A NAME="pgfId=196307"></A><B>assign</B> {A7,A6,A5,A4,A3,A2,A1,A0} = a;
<B>assign</B> {B7,B6,B5,B4,B3,B2,B1,B0} = b;</SPAN> <SPAN CLASS="ComputerLabelV">
<A NAME="pgfId=196309"></A><B>assign</B> s = { S7,S6,S5,S4,S3,S2,S1,S0 };</SPAN>
<SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196310"></A><B>assign</B> S0
= A0^B0^C0 ; // start of level 1: & = AND, ^ = XOR, | = OR, ! = NOT</SPAN>
<SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196311"></A><B>assign</B> S1
= A1^B1^(A0&B0|(A0|B0)&C0) ;</SPAN> <SPAN CLASS="ComputerLabelV">
<A NAME="pgfId=196312"></A><B>assign</B> C2 = A1&B1|(A1|B1)&(A0&B0|(A0|B0)&C0)
;</SPAN> <SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196313"></A><B>assign</B>
C4_2_0 = A3&B3|(A3|B3)&(A2&B2) ; <B>assign</B> C4_2_1 = A3&B3|(A3|B3)&(A2|B2)
;</SPAN> <SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196314"></A><B>assign</B>
S5_4_0 = A5^B5^(A4&B4) ; <B>assign</B> S5_4_1 = A5^B5^(A4|B4) ;</SPAN>
<SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196315"></A><B>assign</B> C6_4_0
= A5&B5|(A5|B5)&(A4&B4) ; <B>assign</B> C6_4_1 = A5&B5|(A5|B5)&(A4|B4)
;</SPAN> <SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196317"></A><B>assign</B>
S2 = A2^B2^C2 ; // start of level 2</SPAN> <SPAN CLASS="ComputerLabelV">
<A NAME="pgfId=196318"></A><B>assign</B> S3 = A3^B3^(A2&B2|(A2|B2)&C2)
;</SPAN> <SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196319"></A><B>assign</B>
S4 = A4^B4^(C4_2_0|C4_2_1&C2) ;</SPAN> <SPAN CLASS="ComputerLabelV">
<A NAME="pgfId=196320"></A><B>assign</B> S5 = S5_4_0& !(C4_2_0|C4_2_1&C2)|S5_4_1&(C4_2_0|C4_2_1&C2)
;</SPAN> <SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196321"></A><B>assign</B>
C6 = C6_4_0|C6_4_1&(C4_2_0|C4_2_1&C2) ;</SPAN> <SPAN CLASS="ComputerLabelV">
<A NAME="pgfId=196322"></A><B>assign</B> S6 = A6^B6^C6 ; // start of level
3</SPAN> <SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196323"></A><B>assign</B>
S7 = A7^B7^(A6&B6|(A6|B6)&C6) ;</SPAN> <SPAN CLASS="ComputerLabelV">
<A NAME="pgfId=196324"></A><B>assign</B> C8 = A7&B7|(A7|B7s)&(A6&B6|(A6|B6)&C6)
;</SPAN> <SPAN CLASS="ComputerLabelV"> <A NAME="pgfId=196325"></A><B>endmodule</B>
</SPAN></TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=165154"></A>Figure 2.26 shows the normalized
delay and area figures for a set of predesigned datapath adders. The data
in Figure 2.26 is from a series of ASIC datapath cell libraries (Compass
Passport) that may be synthesized together with test vectors and simulation
models. We can combine the different adder techniques, but the adders then
lose regularity and become less suited to a datapath implementation.</P>
<P><TABLE BORDER="0" CELLSPACING="2" CELLPADDING="0">
<TR>
<TD><P CLASS="TableFigure"><A NAME="pgfId=177036"></A><IMG SRC="CH02-68.gif"
ALIGN="BASELINE" WIDTH="448" HEIGHT="188" NATURALSIZEFLAG="3"> </TD></TR>
<TR>
<TD><P CLASS="TableFigureTitle"><A NAME="pgfId=177519"></A>FIGURE 2.26 Datapath
adders. This data is from a series of submicron datapath libraries. (a) Delay
normalized to a two-input NAND logic cell delay (approximately equal to
250<SPAN CLASS="White"> </SPAN>ps in a <SPAN CLASS="White"> </SPAN>0.5<SPAN CLASS="White"> </SPAN><SPAN CLASS="Symbol">
m</SPAN> m process). For example, a 64-bit ripple-carry adder (RCA) has
a delay of approximately 30<SPAN CLASS="White"> </SPAN>ns
in a 0.5 <SPAN CLASS="White"> </SPAN><SPAN CLASS="Symbol"> m</SPAN> m process.
The spread in delay is due to variation in delays between different inputs
and outputs. An <SPAN CLASS="EquationVariables"> n</SPAN> -bit RCA has a
delay proportional to <SPAN CLASS="EquationVariables"> n</SPAN> . The delay
of an <SPAN CLASS="EquationVariables"> n</SPAN> -bit carry-select adder
is approximately proportional to log<SPAN CLASS="White"> </SPAN><SUB CLASS="Subscript">
2</SUB> <SPAN CLASS="White"> </SPAN><SPAN CLASS="EquationVariables">
n</SPAN> . The carry-save adder delay is constant (but requires a carry-propagate
adder to complete an addition). (b) In a datapath library the area
of all adders are proportional to the bit size.</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=165446"></A>There are other adders that are
not used in datapaths, but are occasionally useful in ASIC design. A <B>serial
adder</B> is smaller but slower than the <B>parallel adders</B> we have
described [Denyer and Renshaw, 1985]. The <B>carry-completion adder</B>
is a variable delay adder and rarely used in synchronous designs [Sklansky,
1960].</P>
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