ch02.14.htm
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<TD><P CLASS="TableFigureTitle"><A NAME="pgfId=195078"></A>FIGURE 2.22 The
ripple-carry adder (RCA). (a) A conventional RCA. The delay may be
reduced slightly by adding pairs of bubbles as shown to use two-input NAND
gates. (b) An alternative RCA circuit topology using different cells
for odd and even stages and an extra connection between cells. The carry
chain is a fast string of NAND gates (shown in bold).</TD></TR>
</TABLE>
<P CLASS="BodyAfterHead"><A NAME="pgfId=89341"></A>(the carry inputs to
stage zero are C3[1]<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>C4[1]<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>'0').
We can use the RCA of Figure 2.22(b) in a datapath, with standard cells,
or on a gate array.</P>
<P><P CLASS="Body"><A NAME="pgfId=195091"></A>Instead of propagating the
carries through each stage of an RCA, Figure 2.23 shows a different
approach. A <B>carry-save adder</B> (<B> CSA</B> ) cell CSA(A1[<SPAN CLASS="EquationVariables">
i</SPAN> ], A2[<SPAN CLASS="EquationVariables"> i</SPAN> ], A3[<SPAN CLASS="EquationVariables">
i</SPAN> <SPAN CLASS="White"> </SPAN>], CIN,
S1[<SPAN CLASS="EquationVariables"> i</SPAN> ], S2[<SPAN CLASS="EquationVariables">
i</SPAN> ], COUT) has three outputs:</P>
<P><P CLASS="EqnNmbrdAlign"><A NAME="pgfId=177251"></A> S1[<SPAN CLASS="EquationVariables">
i</SPAN> ]<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>CIN(2.51)</P>
<P><P CLASS="EqnNmbrdAlign"><A NAME="pgfId=177252"></A> S2[<SPAN CLASS="EquationVariables">
i</SPAN> ]<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>A1[<SPAN CLASS="EquationVariables">
i</SPAN> ]<SPAN CLASS="White"> </SPAN><SPAN CLASS="Symbol">
</SPAN> <SPAN CLASS="White"> </SPAN>A2[<SPAN CLASS="EquationVariables">
i</SPAN> ]<SPAN CLASS="White"> </SPAN><SPAN CLASS="Symbol">
</SPAN> <SPAN CLASS="White"> </SPAN>A3[<SPAN CLASS="EquationVariables">
i</SPAN> <SPAN CLASS="White"> </SPAN>]<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>PARITY(A1[<SPAN CLASS="EquationVariables">
i</SPAN> ], A2[<SPAN CLASS="EquationVariables"> i</SPAN> ], A3[<SPAN CLASS="EquationVariables">
i</SPAN> <SPAN CLASS="White"> </SPAN>])(2.52)</P>
<P><P CLASS="EqnNmbrdAlign"><A NAME="pgfId=177253"></A> COUT<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>A1[<SPAN CLASS="EquationVariables">
i</SPAN> ]<SPAN CLASS="White"> </SPAN>·<SPAN CLASS="White"> </SPAN>A2[<SPAN CLASS="EquationVariables">
i</SPAN> ]<SPAN CLASS="White"> </SPAN>+<SPAN CLASS="White"> </SPAN>[(A1[<SPAN CLASS="EquationVariables">
i</SPAN> ]<SPAN CLASS="White"> </SPAN>+<SPAN CLASS="White"> </SPAN>A2[<SPAN CLASS="EquationVariables">
i</SPAN> ])<SPAN CLASS="White"> </SPAN>·<SPAN CLASS="White"> </SPAN>A3[<SPAN CLASS="EquationVariables">
i</SPAN> <SPAN CLASS="White"> </SPAN>]]<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>MAJ(A1[<SPAN CLASS="EquationVariables">
i</SPAN> ], A2[<SPAN CLASS="EquationVariables"> i</SPAN> ], A3[<SPAN CLASS="EquationVariables">
i</SPAN> <SPAN CLASS="White"> </SPAN>])(2.53)</P>
<P><P CLASS="Body"><A NAME="pgfId=176807"></A>The inputs, A1, A2, and A3;
and outputs, S1 and S2, are buses. The input, CIN, is the carry from stage
(<SPAN CLASS="EquationVariables"> i</SPAN> <SPAN CLASS="White"> </SPAN><SPAN CLASS="White"> </SPAN>1).
The carry in, CIN, is connected directly to the output bus S1indicated by
the schematic symbol (Figure 2.23a). We connect CIN[0] to VSS. The
output, COUT, is the carry out to stage (<SPAN CLASS="EquationVariables">
i<SPAN CLASS="White"> </SPAN></SPAN> +<SPAN CLASS="White"> </SPAN>1).</P>
<P><P CLASS="Body"><A NAME="pgfId=177617"></A>A 4-bit CSA is shown in Figure 2.23(b).
The arithmetic overflow signal for ones' complement or two's complement
arithmetic, OV, is XOR(COUT[MSB], COUT[MSB<SPAN CLASS="White"> </SPAN><SPAN CLASS="White"> </SPAN>1])
as shown in Figure 2.23(c). In a CSA the carries are "saved"
at each stage and shifted left onto the bus S1. There is thus no carry propagation
and the delay of a CSA is constant. At the output of a CSA we still need
to add the S1 bus (all the saved carries) and the S2 bus (all the sums)
to get an <SPAN CLASS="EquationVariables"> n</SPAN> -bit result using a
final stage that is not shown in Figure 2.23(c). We might regard the
<SPAN CLASS="EquationVariables"> n</SPAN> -bit sum as being encoded in the
two buses, S1 and S2, in the form of the parity and majority functions.</P>
<P><P CLASS="Body"><A NAME="pgfId=176824"></A>We can use a CSA to add multiple
inputsas an example, an adder with four 4-bit inputs is shown in Figure 2.23(d).
The last stage sums two input buses using a <B>carry-propagate adder</B>
(<B> CPA</B> ). We have used an RCA as the CPA in Figure 2.23(d) and
(e), but we can use any type of adder. Notice in Figure 2.23(e) how
the two CSA cells and the RCA cell abut together horizontally to form a
<B>bit slice</B> (or slice) and then the slices are stacked vertically to
form the datapath.</P>
<P><TABLE BORDER="0" CELLSPACING="2" CELLPADDING="0">
<TR>
<TD><P><P CLASS="TableFigure"><A NAME="pgfId=176846"></A> </P>
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<TD><P CLASS="TableFigureTitle"><A NAME="pgfId=176850"></A>FIGURE 2.23 The
carry-save adder (CSA). (a) A CSA cell. (b) A 4-bit CSA. (c) Symbol
for a CSA. (d) A four-input CSA. (e) The datapath for a four-input,
4-bit adder using CSAs with a ripple-carry adder (RCA) as the final stage.
(f) A pipelined adder. (g) The datapath for the pipelined version
showing the pipeline registers as well as the clock control lines that use
m2.</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=99434"></A>We can register the CSA stages
by adding vectors of flip-flops as shown in Figure 2.23(f). This reduces
the adder delay to that of the slowest adder stage, usually the CPA. By
using registers between stages of combinational logic we use <B>pipelining</B>
to increase the speed and pay a price of increased area (for the registers)
and introduce <B>latency</B> . It takes a few clock cycles (the latency,
equal to <SPAN CLASS="EquationVariables"> n</SPAN> clock cycles for an <SPAN CLASS="EquationVariables">
n</SPAN> -stage pipeline) to fill the pipeline, but once it is filled, the
answers emerge every clock cycle. Ferris wheels work much the same way.
When the fair opens it takes a while (latency) to fill the wheel, but once
it is full the people can get on and off every few seconds. (We can also
pipeline the RCA of Figure 2.20. We add <SPAN CLASS="EquationVariables">
<SPAN CLASS="White"> </SPAN>i</SPAN> registers on the A and B inputs
before ADD[<SPAN CLASS="EquationVariables"> i</SPAN> ] and add (<SPAN CLASS="EquationVariables">
n<SPAN CLASS="White"> </SPAN><SPAN CLASS="White"> </SPAN>i</SPAN>
) registers after the output S[<SPAN CLASS="EquationVariables"> i</SPAN>
], with a single register before each C[<SPAN CLASS="EquationVariables">
i</SPAN> ].)</P>
<P><P CLASS="Body"><A NAME="pgfId=170268"></A>The problem with an RCA is
that every stage has to wait to make its carry decision, C[<SPAN CLASS="EquationVariables">
i</SPAN> ], until the previous stage has calculated C[<SPAN CLASS="EquationVariables">
i</SPAN> <SPAN CLASS="White"> </SPAN><SPAN CLASS="White"> </SPAN>1].
If we examine the propagate signals we can bypass this critical path. Thus,
for example, to bypass the carries for bits 47 (stages 58) of an adder we
can compute BYPASS<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>P[4].P[5].P[6].P[7]
and then use a MUX as follows:</P>
<P><P CLASS="EqnNmbrdAlign"><A NAME="pgfId=165250"></A> C[7]<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>(G[7]<SPAN CLASS="White"> </SPAN>+<SPAN CLASS="White"> </SPAN>P[7]<SPAN CLASS="White"> </SPAN>·<SPAN CLASS="White"> </SPAN>C[6])<SPAN CLASS="White"> </SPAN>·<SPAN CLASS="White"> </SPAN>BYPASS'<SPAN CLASS="White"> </SPAN>+<SPAN CLASS="White"> </SPAN>C[3]<SPAN CLASS="White"> </SPAN>·<SPAN CLASS="White"> </SPAN>BYPASS.(2.54)</P>
<P><P CLASS="Body"><A NAME="pgfId=165238"></A>Adders based on this principle
are called <B>carry-bypass adders</B> (<B> CBA</B> ) [Sato et al., 1992].
Large, custom adders employ <B>Manchester-carry chains</B> to compute the
carries and the bypass operation using TGs or just pass transistors [Weste
and Eshraghian, 1993, pp. 530531]. These types of carry chains may
be part of a predesigned ASIC adder cell, but are not used by ASIC designers.</P>
<P><P CLASS="Body"><A NAME="pgfId=177373"></A>Instead of checking the propagate
signals we can check the inputs. For example we can compute SKIP<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>(A[<SPAN CLASS="EquationVariables">
i</SPAN> <SPAN CLASS="White"> </SPAN><SPAN CLASS="White"> </SPAN>1]<SPAN CLASS="White"> </SPAN><SPAN CLASS="Symbol">
</SPAN> <SPAN CLASS="White"> </SPAN>B[<SPAN CLASS="EquationVariables">
i</SPAN> <SPAN CLASS="White"> </SPAN><SPAN CLASS="White"> </SPAN>1])<SPAN CLASS="White"> </SPAN><SPAN CLASS="White"> </SPAN>+<SPAN CLASS="White"> </SPAN>(A[<SPAN CLASS="EquationVariables">
i</SPAN> ]<SPAN CLASS="White"> </SPAN><SPAN CLASS="Symbol">
</SPAN> <SPAN CLASS="White"> </SPAN>B[<SPAN CLASS="EquationVariables">
i</SPAN> ]<SPAN CLASS="White"> </SPAN>) and then use a 2:1 MUX to select
C[<SPAN CLASS="EquationVariables"> i</SPAN> ]. Thus,</P>
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