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<H2>2.5.1 Latch</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=88875"></A>Figure 2.17(a)
shows a sequential logic cella <B>latch</B> . The internal clock signals,
CLKN (N for negative) and CLKP (P for positive), are generated from the
system clock, CLK, by two inverters (I4 and I5) that are part of every latch
cellit is usually too dangerous to have these signals supplied externally,
even though it would save space.</P>
<P><TABLE BORDER="0" CELLSPACING="2" CELLPADDING="0">
<TR>
<TD><P CLASS="TableFigure"><A NAME="pgfId=56228"></A><IMG SRC="CH02-59.gif"
ALIGN="BASELINE" WIDTH="448" HEIGHT="176" NATURALSIZEFLAG="3"> </TD></TR>
<TR>
<TD><P CLASS="TableFigureTitle"><A NAME="pgfId=56231"></A>FIGURE 2.17 CMOS
latch. (a) A positive-enable latch using transmission gates without
output buffering, the enable (clock) signal is buffered inside the latch.
(b) A positive-enable latch is transparent while the enable is high.
(c) The latch stores the last value at D when the enable goes low.</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=56203"></A>To emphasize the difference between
a latch and flip-flop, sometimes people refer to the clock input of a latch
as an <B>enable</B> . This makes sense when we look at Figure 2.17(b),
which shows the operation of a latch. When the clock input is high, the
latch is <B>transparent</B> changes at the D input appear at the output
Q (quite different from a flip-flop as we shall see). When the enable (clock)
goes low (Figure 2.17c), inverters I2 and I3 are connected together,
forming a storage loop that holds the last value on D until the enable goes
high again. The storage loop will hold its state as long as power is on;
we call this a <B>static</B> latch. A <B>sequential logic cell</B> is different
from a combinational cell because it has this feature of storage or memory.</P>
<P><P CLASS="Body"><A NAME="pgfId=55877"></A>Notice that the output Q is
unbuffered and connected directly to the output of I2 (and the input of
I3), which is a storage node. In an ASIC library we are conservative and
add an inverter to buffer the output, isolate the sensitive storage node,
and thus invert the sense of Q. If we want both Q and QN we have to add
two inverters to the circuit of Figure 2.17(a). This means that a latch
requires seven inverters and two TGs (4.5 gates).</P>
<P><P CLASS="Body"><A NAME="pgfId=56219"></A>The latch of Figure 2.17(a)
is a positive-enable D latch, active-high D latch, or transparent-high D
latch (sometimes people also call this a D-type latch). A negative-enable
(active-low) D latch can be built by inverting all the clock polarities
in Figure 2.17(a) (swap CLKN for CLKP and vice-versa).</P>
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