📄 ch02.2.htm
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(2.22)</P>
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If the CSN and CSP masks do not overlap, it is possible to save a mask by using one implant mask (CSN or CSP) for the other type (CSP or CSN). We can do this by using a <SPAN CLASS="Definition">
positive resist</SPAN>
(the pattern of resist remaining after developing is the same as the dark areas on the mask) for one implant step and a <SPAN CLASS="Definition">
negative resist</SPAN>
(vice versa) for the other step. However, because of the poor resolution of negative resist and because of difficulties in generating the implant masks automatically from the drawn diffusions (especially when opposite diffusion types are drawn close to each other or touching), it is now common to draw both implant masks as well as the two diffusion layers.</P>
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It is important to remember that, even though poly is above diffusion, the polysilicon is deposited first and acts like masking tape. It is rather like airbrushing a stripe—you use masking tape and spray everywhere without worrying about making straight lines. The edges of the pattern will align to the edge of the tape. Here the analogy ends because the poly is left in place. Thus, </P>
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<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-diffusion (silicon) = (ndiff (drawn)) <SPAN CLASS="Symbol">
∧</SPAN>
(<SPAN CLASS="Symbol">
ÿ</SPAN>
poly (drawn)) and</P>
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(2.23)</P>
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<P CLASS="TableEqnLeft">
<A NAME="pgfId=378837">
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<SPAN CLASS="EmphasisPrefix">
p</SPAN>
-diffusion (silicon) = (pdiff (drawn)) <SPAN CLASS="Symbol">
∧</SPAN>
(<SPAN CLASS="Symbol">
ÿ</SPAN>
poly (drawn)) .</P>
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(2.24)</P>
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<P CLASS="Body">
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<SPAN CLASS="EmphasisPrefix">
</SPAN>
In the ASIC industry the names nplus, <SPAN CLASS="EmphasisPrefix">
n</SPAN>
+, and <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-diffusion (as well as the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type equivalents) are used in various ways. These names may refer to either the drawn diffusion layer (that we call ndiff), the mask (CSN), or the doped region on the silicon (the intersection of the active and implant mask that we call <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-diffusion)—very confusing.</P>
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The source and drain are often formed from two separate implants. The first is a light implant close to the edge of the gate, the second a heavier implant that forms the rest of the source or drain region. The separate diffusions reduce the electric field near the drain end of the channel. Tailoring the device characteristics in this fashion is known as <SPAN CLASS="Definition">
drain engineering</SPAN>
and a process including these steps is referred to as an <SPAN CLASS="Definition">
LDD process</SPAN>
, for <SPAN CLASS="Definition">
lightly doped drain</SPAN>
<SPAN CLASS="Bold">
;</SPAN>
the first light implant is known as an <SPAN CLASS="Definition">
LDD diffusion</SPAN>
or LDD implant.</P>
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FIGURE 2.8 Drawn layers and an example set of black-and-white stipple patterns for a CMOS process. On top are the patterns as they appear in layout. Underneath are the magnified 8-by-8 pixel patterns. If we are trying to simplify layout we may use solid black or white for contact and vias. If we have contacts and vias placed on top of one another we may use stipple patterns or other means to help distinguish between them. Each stipple pattern is transparent, so that black shows through from underneath when layers are superimposed. There are no standards for these patterns. </P>
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<P CLASS="Body">
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Figure 2.8 shows a <SPAN CLASS="Definition">
stipple-pattern</SPAN>
matrix for a CMOS process. When we draw layout you can see through the layers—all the stipple patterns are OR’ed together. Figure 2.9 shows the transistor layers as they appear in layout (drawn using the patterns from Figure 2.8) and as they appear on the silicon. Figure 2.10 shows the same thing for the interconnect layers.</P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
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</A>
<IMG SRC="CH02-21.gif" ALIGN="BASELINE">
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
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FIGURE 2.9 The transistor layers. (a) A <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor as drawn in layout. (b) The corresponding silicon cross section (the heavy lines in part a show the cuts). This is how a <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor would look just after completing the source and drain implant steps.</P>
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<TD ROWSPAN="1" COLSPAN="1">
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FIGURE 2.10 The interconnect layers. (a) Metal layers as drawn in layout. (b) The corresponding structure (as it might appear in a scanning-electron micrograph). The insulating layers between the metal layers are not shown. Contact is made to the underlying silicon through a platinum barrier layer. Each via consists of a tungsten plug. Each metal layer consists of a titanium–tungsten and aluminum–copper sandwich. Most deep submicron CMOS processes use metal structures similar to this. The scale, rounding, and irregularity of the features are realistic.</P>
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<DIV>
<IMG SRC="CH02-22.gif">
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<DIV>
<H3 CLASS="Heading2">
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2.2.1 Sheet Resistance</H3>
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Tables 2.3 and 2.4 show the sheet resistance for each conducting layer (in decreasing order of resistance) for two different generations of CMOS process.</P>
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<TD ROWSPAN="1" COLSPAN="3">
<P CLASS="TableTitle">
<A NAME="pgfId=214789">
</A>
TABLE 2.3 Sheet resistance (1 <SPAN CLASS="Symbol">
m</SPAN>
m CMOS).</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=214795">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="3">
<P CLASS="TableTitle">
<A NAME="pgfId=214799">
</A>
TABLE 2.4 Sheet resistance (0.35<SPAN CLASS="Symbol">
m</SPAN>
m CMOS).</P>
</TD>
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<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
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<SPAN CLASS="TableHeads">
Layer</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=214807">
</A>
<SPAN CLASS="TableHeads">
Sheet</SPAN>
</P>
<P CLASS="TableFirst">
<A NAME="pgfId=214808">
</A>
<SPAN CLASS="TableHeads">
resistance</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=214810">
</A>
<SPAN CLASS="TableHeads">
Units</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=214812">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=214814">
</A>
<SPAN CLASS="TableHeads">
Layer</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=214816">
</A>
<SPAN CLASS="TableHeads">
Sheet</SPAN>
</P>
<P CLASS="TableFirst">
<A NAME="pgfId=214817">
</A>
<SPAN CLASS="TableHeads">
resistance</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=214819">
</A>
<SPAN CLASS="TableHeads">
Units</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214821">
</A>
<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-well</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214823">
</A>
1.15 ± 0.25</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214825">
</A>
k<SPAN CLASS="Symbol">
W</SPAN>
/ square</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214827">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214829">
</A>
<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-well </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214831">
</A>
1 ± 0.4</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214833">
</A>
k<SPAN CLASS="Symbol">
W</SPAN>
/ square</P>
</TD>
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<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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poly</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214838">
</A>
3.5 ± 2.0</P>
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<SPAN CLASS="Symbol">
W</SPAN>
/ square</P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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poly</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214846">
</A>
10 ± 4.0</P>
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<SPAN CLASS="Symbol">
W</SPAN>
/ square</P>
</TD>
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<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214850">
</A>
<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-diffusion</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214852">
</A>
75 ± 20</P>
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<SPAN CLASS="Symbol">
W</SPAN>
/ square</P>
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<P CLASS="Table">
<A NAME="pgfId=214856">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214858">
</A>
<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-diffusion</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214860">
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3.5 ± 2.0</P>
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<SPAN CLASS="Symbol">
W</SPAN>
/ square</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214864">
</A>
<SPAN CLASS="EmphasisPrefix">
p</SPAN>
-diffusion </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214866">
</A>
140 ± 40</P>
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<SPAN CLASS="Symbol">
W</SPAN>
/ square</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214870">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214872">
</A>
<SPAN CLASS="EmphasisPrefix">
p</SPAN>
-diffusion </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214874">
</A>
2.5 ± 1.5</P>
</TD>
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<P CLASS="Table">
<A NAME="pgfId=214876">
</A>
<SPAN CLASS="Symbol">
W</SPAN>
/ square</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214878">
</A>
m1/2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214881">
</A>
70± 6</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214883">
</A>
m<SPAN CLASS="Symbol">
W</SPAN>
/ square</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=214885">
</A>
</P>
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