ch02.2.htm

介绍asci设计的一本书

	glass </P>
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 </A>
	= glass</P>
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	passivation, overglass, pad</P>
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COG</P>
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Table&nbsp;2.2 shows the mask layers (and their relation to the drawn layers) for a submicron, silicon-gate, three-level metal, self-aligned, CMOS <SPAN CLASS="Definition">
process</SPAN>
. A process in which the effective gate length is less than 1 <SPAN CLASS="Symbol">
m</SPAN>
m is referred to as a <SPAN CLASS="Definition">
submicron process</SPAN>
. Gate lengths below 0.35 <SPAN CLASS="Symbol">
m</SPAN>
m are considered in the <SPAN CLASS="Definition">
deep-submicron</SPAN>
 regime. </P>
<P CLASS="Body">
<A NAME="pgfId=206794">
 </A>
Figure&nbsp;2.7 shows the layers that we draw to define the masks for the logic cell of Figure&nbsp;1.3. Potential confusion arises because we like to keep layout simple but maintain a &#8220;what you see is what you get&#8221; (WYSIWYG) approach. This means that the drawn layers do not correspond directly to the masks in all cases. </P>
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<IMG SRC="CH02-9.gif" ALIGN="BASELINE">
&nbsp;</P>
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&nbsp;</P>
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<IMG SRC="CH02-11.gif" ALIGN="BASELINE">
&nbsp;</P>
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<IMG SRC="CH02-12.gif" ALIGN="BASELINE">
&nbsp;</P>
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(a) nwell</P>
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(b) pwell</P>
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(c) ndiff</P>
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(d) pdiff</P>
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&nbsp;</P>
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&nbsp;</P>
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&nbsp;</P>
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&nbsp;</P>
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(e) poly</P>
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(f) contact</P>
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(g) m1</P>
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(h) via</P>
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&nbsp;</P>
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&nbsp;</P>
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&nbsp;</P>
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&nbsp;</P>
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(i) m2</P>
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(j) cell</P>
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(k) phantom</P>
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&nbsp;</P>
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&nbsp;</P>
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&nbsp;</P>
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&nbsp;</P>
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&nbsp;</P>
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<P CLASS="TableFigureTitle">
<A NAME="pgfId=149681">
 </A>
FIGURE&nbsp;2.7&nbsp;The standard cell shown in Figure&nbsp;1.3. (a)&#8211;(i)&nbsp;The drawn layers that define the masks. The active mask is the union of the ndiff and pdiff drawn layers. The <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-diffusion implant and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-diffusion implant masks are bloated versions of the ndiff and pdiff drawn layers. (j)&nbsp;The complete cell layout. (k)&nbsp;The phantom cell layout. Often an ASIC vendor hides the details of the internal cell construction. The phantom cell is used for layout by the customer and then &#8220;instantiated&#8221; by the ASIC vendor after layout is complete. This layout uses grayscale stipple patterns to distinguish between layers. </P>
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<P CLASS="Body">
<A NAME="pgfId=32075">
 </A>
We can construct wells in a CMOS process in several ways. In an <SPAN CLASS="Definition">
n-well process</SPAN>
, the substrate is <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type (the wafer itself) and we use an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-well mask to build the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-well. We do not need a <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-well mask because there are no <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-wells in an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-well process&#8212;the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistors all sit in the substrate (the wafer)&#8212;but we often draw the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-well layer as though it existed. In a <SPAN CLASS="Definition">
p-well process</SPAN>
 we use a <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-well mask to make the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-wells and the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-wells are the substrate. In a <SPAN CLASS="Definition">
twin-tub</SPAN>
 (or <SPAN CLASS="Definition">
twin-well</SPAN>
) process, we create individual wells for both types of transistors, and neither well is the substrate (which may be either <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-type or <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type). There are even <SPAN CLASS="Definition">
triple-well</SPAN>
 processes used to achieve even more control over the transistor performance. Whatever process that we use we must connect all the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-wells to the most positive potential on the chip, normally VDD, and all the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-wells to VSS; otherwise we may forward bias the bulk to source/drain <SPAN CLASS="EmphasisPrefix">
pn</SPAN>
-junctions. The bulk connections for CMOS transistors are not usually drawn in digital circuit schematics, but these <SPAN CLASS="Definition">
substrate contacts </SPAN>
(<SPAN CLASS="Definition">
well contacts</SPAN>
 or<SPAN CLASS="Definition">
 tub&nbsp;ties</SPAN>
) are very important. After we make the well(s), we grow a layer (approximately 1500 &Aring;) of Si<SUB CLASS="Subscript">
3</SUB>
N<SUB CLASS="Subscript">
4 </SUB>
over the wafer. The <SPAN CLASS="Definition">
active</SPAN>
 mask (CAA) leaves this nitride layer only in the active areas that will later become transistors or substrate contacts. Thus &nbsp;</P>
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<P CLASS="TableEqnLeft">
<A NAME="pgfId=378707">
 </A>
CAA (mask) = ndiff (drawn) <SPAN CLASS="Symbol">
&#8744;</SPAN>
 pdiff (drawn) ,</P>
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<P CLASS="TableEqnNumber">
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(2.18)</P>
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<P CLASS="BodyAfterHead">
<A NAME="pgfId=149254">
 </A>
the <SPAN CLASS="Symbol">
&#8744;</SPAN>
 symbol represents OR (union) of the two drawn layers, ndiff and pdiff. Everything outside the active areas is known as the field region, or just <SPAN CLASS="Definition">
field</SPAN>
. </P>
<P CLASS="Body">
<A NAME="pgfId=190427">
 </A>
Next we implant the substrate to prevent unwanted transistors from forming in the field region&#8212;this is the <SPAN CLASS="Definition">
field implant</SPAN>
 or <SPAN CLASS="Definition">
channel-stop implant</SPAN>
. The nitride over the active areas acts as an implant mask and we may use another field-implant mask at this step also. Following this we grow a thick (approximately 5000 &Aring;) layer of SiO<SUB CLASS="Subscript">
2</SUB>
, the <SPAN CLASS="Definition">
field oxide</SPAN>
 (<SPAN CLASS="Definition">
FOX</SPAN>
). The FOX will not grow over the nitride areas. When we strip the nitride we are left with FOX in the areas we do <SPAN CLASS="Emphasis">
not</SPAN>
 want to dope the silicon. Following this we deposit, dope, mask, and etch the poly gate material, CPG (mask) = poly (drawn). Next we create the doped regions that form the sources, drains, and substrate contacts using ion implantation. The poly gate functions like masking tape in these steps. One implant (using phosphorous or arsenic ions) forms the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-type source/drain for the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistors and <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-type substrate contacts (CSN). A second implant (using boron ions) forms the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type source&#8211;drain for the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistors and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type substrate contacts (CSP). These implants are masked as follows &nbsp;</P>
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<P CLASS="TableEqnLeft">
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CSN (mask) = grow (ndiff (drawn)),</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=378746">
 </A>
(2.19)</P>
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<P CLASS="TableEqnLeft">
<A NAME="pgfId=378761">
 </A>
CSP (mask) = grow (pdiff (drawn)),</P>
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<P CLASS="TableEqnNumber">
<A NAME="pgfId=378763">
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(2.20)</P>
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<P CLASS="BodyAfterHead">
<A NAME="pgfId=146992">
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where &#8220;grow&#8221; means that we expand or <SPAN CLASS="Definition">
bloat</SPAN>
 the drawn ndiff and drawn pdiff layers slightly (usually by a few <SPAN CLASS="Symbol">
l</SPAN>
). </P>
<P CLASS="Body">
<A NAME="pgfId=206559">
 </A>
During implantation the <SPAN CLASS="Definition">
dopant</SPAN>
 ions are blocked by the resist pattern defined by the CSN and CSP masks. The CSN mask thus prevents the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-type regions being implanted with <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type dopants (and vice versa for the CSP mask). As we shall see, the CSN and CSP masks are not intended to define the edges of the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-type and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type regions. Instead these two masks function more like newspaper that prevents paint from spraying everywhere. The dopant ions are also blocked from reaching the silicon surface by the poly gates and this aligns the edge of the source and drain regions to the edges of the gates (we call this a <SPAN CLASS="Definition">
self-aligned process</SPAN>
). In addition, the implants are blocked by the FOX and this defines the outside edges of the source, drain, and substrate contact regions. </P>
<P CLASS="Body">
<A NAME="pgfId=149035">
 </A>
The only areas of the silicon surface that are doped <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-type are &nbsp;</P>
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<P CLASS="TableEqnLeft">
<A NAME="pgfId=378775">
 </A>
<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-diffusion (silicon) = (CAA (mask) <SPAN CLASS="Symbol">
&#8743;</SPAN>
 CSN (mask)) <SPAN CLASS="Symbol">
&#8743;</SPAN>
 (<SPAN CLASS="Symbol">
&yuml;</SPAN>
 CPG (mask))  ;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=378777">
 </A>
(2.21)</P>
</TD>
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</TABLE>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=149114">
 </A>
<SPAN CLASS="EmphasisPrefix">
</SPAN>
where the <SPAN CLASS="Symbol">
&#8743;</SPAN>
 symbol represents AND (the intersection of two layers); and the <SPAN CLASS="Symbol">
&yuml;</SPAN>
 symbol represents NOT. </P>
<P CLASS="Body">
<A NAME="pgfId=378821">
 </A>
Similarly, the only regions that are doped <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type are &nbsp;</P>
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<P CLASS="TableEqnLeft">
<A NAME="pgfId=378818">
 </A>
<SPAN CLASS="EmphasisPrefix">
p</SPAN>
-diffusion (silicon) = (CAA (mask) <SPAN CLASS="Symbol">
&#8743;</SPAN>
 CSP (mask))<SPAN CLASS="Symbol">
 &#8743; </SPAN>
(<SPAN CLASS="Symbol">
&yuml;</SPAN>
 CPG (mask)) .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">