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<TITLE> 2.2 The CMOS Process</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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2.2 The CMOS Process</H1>
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Figure 2.6 outlines the steps to create an integrated circuit. The starting material is silicon, Si, refined from quartzite (with less than 1 impurity in 10<SUP CLASS="Superscript">
10</SUP>
silicon atoms). We draw a single-crystal silicon <SPAN CLASS="Definition">
boule</SPAN>
(or ingot) from a crucible containing a melt at approximately 1500 °C (the melting point of silicon at 1 atm. pressure is 1414 °C). This method is known as Czochralski growth. Acceptor (<SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type) or donor (<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-type) dopants may be introduced into the melt to alter the type of silicon grown. </P>
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The boule is sawn to form thin circular wafers (6, 8, or 12 inches in diameter, and typically 600 <SPAN CLASS="Symbol">
m</SPAN>
m thick), and a flat is ground (the primary flat), perpendicular to the <110> crystal axis—as a “this edge down” indication. The boule is drawn so that the wafer surface is either in the (111) or (100) crystal planes. A smaller secondary flat indicates the wafer crystalline orientation and doping type. A typical submicron CMOS processes uses <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type (100) wafers with a resistivity of approximately 10 <SPAN CLASS="Symbol">
W</SPAN>
cm—this type of wafer has two flats, 90° apart. Wafers are made by chemical companies and sold to the IC manufacturers. A blank 8-inch wafer costs about $100.</P>
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To begin IC fabrication we place a batch of wafers (a <SPAN CLASS="Definition">
wafer lot</SPAN>
) on a <SPAN CLASS="Definition">
boat </SPAN>
and grow a layer (typically a few thousand angstroms) of <SPAN CLASS="Definition">
silicon dioxide</SPAN>
, SiO<SUB CLASS="Subscript">
2</SUB>
, using a furnace. Silicon is used in the semiconductor industry not so much for the properties of silicon, but because of the physical, chemical, and electrical properties of its native oxide, SiO<SUB CLASS="Subscript">
2</SUB>
. An IC fabrication <SPAN CLASS="Definition">
process</SPAN>
contains a series of masking steps (that in turn contain other steps) to create the layers that define the transistors and metal interconnect.</P>
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FIGURE 2.6 IC fabrication. Grow crystalline silicon (1); make a wafer (2–3); grow a silicon dioxide (oxide) layer in a furnace (4); apply liquid photoresist (resist) (5); mask exposure (6); a cross-section through a wafer showing the developed resist (7); etch the oxide layer (8); ion implantation (9–10); strip the resist (11); strip the oxide (12). Steps similar to 4–12 are repeated for each layer (typically 12–20 times for a CMOS process). </P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=178826">
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Each masking step starts by spinning a thin layer (approximately 1 <SPAN CLASS="Symbol">
m</SPAN>
m) of liquid photoresist (<SPAN CLASS="Definition">
resist</SPAN>
) onto each wafer. The wafers are baked at about 100 °C to remove the solvent and harden the resist before being exposed to ultraviolet (UV) light (typically less than 200 nm wavelength) through a <SPAN CLASS="Definition">
mask</SPAN>
. The UV light alters the structure of the resist, allowing it to be removed by developing. The exposed oxide may then be <SPAN CLASS="Definition">
etched</SPAN>
(removed). Dry <SPAN CLASS="Definition">
plasma etching</SPAN>
etches in the vertical direction much faster than it does horizontally (an <SPAN CLASS="Definition">
anisotropic</SPAN>
etch). Wet etch techniques are usually <SPAN CLASS="Definition">
isotropic</SPAN>
. The resist functions as a mask during the etch step and transfers the desired pattern to the oxide layer.</P>
<P CLASS="Body">
<A NAME="pgfId=195463">
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Dopant ions are then introduced into the exposed silicon areas. Figure 2.6 illustrates the use of <SPAN CLASS="Definition">
ion implantation</SPAN>
. An <SPAN CLASS="Definition">
ion implanter</SPAN>
is a cross between a TV and a mass spectrometer and fires dopant ions into the silicon wafer. Ions can only penetrate materials to a depth (the <SPAN CLASS="Definition">
range</SPAN>
, normally a few microns) that depends on the closely controlled <SPAN CLASS="Definition">
implant energy</SPAN>
(measured in keV—usually between 10 and 100 keV; an electron volt, 1 eV, is 1.6 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–19</SUP>
J). By using layers of resist, oxide, and polysilicon we can prevent dopant ions from reaching the silicon surface and thus block the silicon from receiving an <SPAN CLASS="Definition">
implant</SPAN>
. We control the doping level by counting the number of ions we implant (by integrating the ion-beam current). The <SPAN CLASS="Definition">
implant dose</SPAN>
is measured in atoms/cm<SUP CLASS="Superscript">
2</SUP>
(typical doses are from 10<SUP CLASS="Superscript">
13</SUP>
to 10<SUP CLASS="Superscript">
15</SUP>
cm<SUP CLASS="Superscript">
–2</SUP>
). As an alternative to ion implantation we may instead strip the resist and introduce dopants by diffusion from a gaseous source in a furnace. </P>
<P CLASS="Body">
<A NAME="pgfId=206789">
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Once we have completed the transistor diffusion layers we can deposit layers of other materials. Layers of polycrystalline silicon (polysilicon or <SPAN CLASS="Definition">
poly</SPAN>
), SiO<SUB CLASS="Subscript">
2</SUB>
, and silicon nitride (Si<SUB CLASS="Subscript">
3</SUB>
N<SUB CLASS="Subscript">
4</SUB>
), for example, may be deposited using <SPAN CLASS="Definition">
chemical vapor deposition</SPAN>
(<SPAN CLASS="Definition">
CVD</SPAN>
). Metal layers can be deposited using <SPAN CLASS="Definition">
sputtering</SPAN>
. All these layers are patterned using masks and similar <SPAN CLASS="Definition">
photolithography</SPAN>
steps to those shown in Figure 2.6.</P>
<TABLE>
<TR>
<TH ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=195486">
</A>
TABLE 2.2 CMOS process layers.</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=195494">
</A>
Mask/layer name </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=195496">
</A>
Derivation from drawn layers</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=195498">
</A>
Alternative names for mask/layer</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=195500">
</A>
MOSIS mask label</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195503">
</A>
<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-well</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195509">
</A>
= nwell<A HREF="#pgfId=195508" CLASS="footnote">
1</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195513">
</A>
bulk, substrate, tub, <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-tub, moat</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195516">
</A>
CWN</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195519">
</A>
<SPAN CLASS="EmphasisPrefix">
p</SPAN>
-well</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195524">
</A>
= pwell<SUP CLASS="Superscript">
1</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195527">
</A>
bulk, substrate, tub, <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-tub, moat</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195530">
</A>
CWP</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195533">
</A>
active</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195535">
</A>
= pdiff + ndiff</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195539">
</A>
thin oxide, thinox, island, gate oxide</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195542">
</A>
CAA</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195545">
</A>
polysilicon</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195547">
</A>
= poly</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195551">
</A>
poly, gate</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195554">
</A>
CPG</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195561">
</A>
<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-diffusion implant<A HREF="#pgfId=195560" CLASS="footnote">
2</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195563">
</A>
= grow (ndiff)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195569">
</A>
ndiff, <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-select, nplus, n+ </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195572">
</A>
CSN</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195578">
</A>
<SPAN CLASS="EmphasisPrefix">
p</SPAN>
-diffusion implant<SUP CLASS="Superscript">
2</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195580">
</A>
= grow (pdiff)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195586">
</A>
pdiff, <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-select, pplus, p+ </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195589">
</A>
CSP</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195592">
</A>
contact</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195594">
</A>
= contact</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195599">
</A>
contact cut, poly contact, diffusion contact</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195606">
</A>
CCP and CCA<A HREF="#pgfId=195605" CLASS="footnote">
3</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195609">
</A>
metal1 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195611">
</A>
= m1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195615">
</A>
first-level metal </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195618">
</A>
CMF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195621">
</A>
metal2 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195623">
</A>
= m2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195627">
</A>
second-level metal </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195630">
</A>
CMS</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195633">
</A>
via2 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195635">
</A>
= via2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195639">
</A>
metal2/metal3 via, m2/m3 via</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195642">
</A>
CVS</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=201091">
</A>
metal3 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195647">
</A>
= m3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195651">
</A>
third-level metal </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195654">
</A>
CMT</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=195657">
</A>
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