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<TITLE> 2.5.3 Clocked Inverter</TITLE>
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<H2>2.5.3 Clocked Inverter</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=143079"></A>Figure 2.19
shows how we can derive the structure of a <B>clocked inverter</B> from
the series combination of an inverter and a TG. The arrows in Figure 2.19(b)
represent the flow of current when the inverter is charging (<SPAN CLASS="EquationVariables">
I</SPAN> <SUB CLASS="SubscriptVariable"> R</SUB> ) or discharging (<SPAN CLASS="EquationVariables">
I</SPAN> <SUB CLASS="SubscriptVariable"> F</SUB> ) a load capacitance through
the TG. We can break the connection between the inverter cells and use the
circuit of Figure 2.19(c) without substantially affecting the operation
of the circuit. The symbol for the clocked inverter shown in Figure 2.19(d)
is common, but by no means a standard.</P>
<P><TABLE BORDER="0" CELLSPACING="2" CELLPADDING="0">
<TR>
<TD><P><P CLASS="TableFigure"><A NAME="pgfId=143096"></A> </P>
<P><IMG SRC="CH02-61.gif" WIDTH="356" HEIGHT="180" NATURALSIZEFLAG="3"
ALIGN="BOTTOM"></TD></TR>
<TR>
<TD><P CLASS="TableFigureTitle"><A NAME="pgfId=143099"></A>FIGURE 2.19 Clocked
inverter. (a) An inverter plus transmission gate (TG). (b) The
current flow in the inverter and TG allows us to break the connection between
the transistors in the inverter. (c) Breaking the connection forms
a clocked inverter. (d) A common symbol.</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=143100"></A>We can use the clocked inverter
to replace the inverter–TG pairs in latches and flip-flops. For example,
we can replace one or both of the inverters I1 and I3 (together with the
TGs that follow them) in Figure 2.17(a) by clocked inverters. There
is not much to choose between the different implementations in this case,
except that layout may be easier for the clocked inverter versions (since
there is one less connection to make).</P>
<P><P CLASS="Body"><A NAME="pgfId=143104"></A>More interesting is the flip-flop
design: We can only replace inverters I1, I3, and I7 (and the TGs that follow
them) in Figure 2.18(a) by clocked inverters. We cannot replace inverter
I6 because it is not directly connected to a TG. We can replace the TG attached
to node M with a clocked inverter, and this will invert the sense of the
output Q, which thus becomes QN. Now the clock-to-Q delay will be slower
than clock-to-QN, since Q (which was QN) now comes one inverter later than
QN.</P>
<P><P CLASS="Body"><A NAME="pgfId=143108"></A>If we wish to build a flip-flop
with a fast clock-to-QN delay it may be better to build it using clocked
inverters and use inverters with TGs for a flip-flop with a fast clock-to-Q
delay. In fact, since we do not always use both Q and QN outputs of a flip-flop,
some libraries include Q only or QN only flip-flops that are slightly smaller
than those with both polarity outputs. It is slightly easier to layout clocked
inverters than an inverter plus a TG, so flip-flops in commercial libraries
include a mixture of clocked-inverter and TG implementations.</P>
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