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<H2>2.7 I/O Cells</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=110722"></A>Figure 2.33
shows a three-state bidirectional output buffer (Tri-State<SUP CLASS="Superscript">®</SUP>
is a registered trademark of National Semiconductor). When the
output enable (OE) signal is high, the circuit functions as a noninverting
buffer driving the value of DATAin onto the I/O pad. When OE is low, the
output transistors or <B>drivers</B> , M1 and M2, are disconnected. This
allows multiple drivers to be connected on a bus. It is up to the designer
to make sure that a bus never has two driversa problem known as <B>contention</B>
.</P>
<P><P CLASS="Body"><A NAME="pgfId=162176"></A>In order to prevent the problem
opposite to contentiona bus floating to an intermediate voltage when there
are no bus driverswe can use a <B>bus keeper</B> or <B>bus-hold</B> cell
(TI calls this Bus-Friendly logic). A bus keeper normally acts like two
weak (low drive-strength) cross-coupled inverters that act as a latch to
retain the last logic state on the bus, but the latch is weak enough that
it may be driven easily to the opposite state. Even though bus keepers act
like latches, and will simulate like latches, they should not be used as
latches, since their drive strength is weak.</P>
<P><P CLASS="Body"><A NAME="pgfId=110735"></A>Transistors M1 and M2 in Figure 2.33
have to drive large off-chip loads. If we wish to change the voltage on
a <SPAN CLASS="EquationVariables"> C</SPAN><SPAN CLASS="White"> </SPAN>=
<SPAN CLASS="White"> </SPAN>200<SPAN CLASS="White"> </SPAN>pF
load by 5<SPAN CLASS="White"> </SPAN>V in 5<SPAN CLASS="White"> </SPAN>ns
(a <B>slew rate</B> of 1<SPAN CLASS="White"> </SPAN>Vns<SUP CLASS="Superscript">
–1</SUP> ) we will require a current in the output transistors of</P>
<P><P CLASS="Equation"><A NAME="pgfId=110740"></A><IMG SRC="CH02-113.gif"
ALIGN="BASELINE" WIDTH="242" HEIGHT="24" NATURALSIZEFLAG="3"> A or 200<SPAN CLASS="White"> </SPAN>mA.</P>
<P><P CLASS="Body"><A NAME="pgfId=110742"></A>Such large currents flowing
in the output transistors must also flow in the power supply bus and can
cause problems. There is always some inductance in series with the power
supply, between the point at which the supply enters the ASIC package and
reaches the power bus on the chip. The inductance is due to the bond wire,
lead frame, and package pin. If we have a power-supply inductance of 2<SPAN CLASS="White"> </SPAN>nH
and a current changing from zero to 1<SPAN CLASS="White"> </SPAN>A
(32 I/O cells on a bus switching at 30<SPAN CLASS="White"> </SPAN>mA
each) in 5<SPAN CLASS="White"> </SPAN>ns, we
will have a voltage spike on the power supply (called <B>power-supply bounce</B>
) of <SPAN CLASS="EquationVariables"> L</SPAN> (d<SPAN CLASS="EquationVariables">
I</SPAN> /d<SPAN CLASS="EquationVariables"> t</SPAN> )<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>(2<SPAN CLASS="White"> </SPAN><SPAN CLASS="Symbol">
¥</SPAN> <SPAN CLASS="White"> </SPAN>10<SUP CLASS="Superscript">
–9</SUP> )(1/(5<SPAN CLASS="White"> </SPAN><SPAN CLASS="Symbol">
¥</SPAN> <SPAN CLASS="White"> </SPAN>10<SUP CLASS="Superscript">
–9</SUP> ))<SPAN CLASS="White"> </SPAN>=<SPAN CLASS="White"> </SPAN>0.4<SPAN CLASS="White"> </SPAN>V.</P>
<P><P CLASS="Body"><A NAME="pgfId=110748"></A>We do several things to alleviate
this problem: We can limit the number of <B>simultaneously switching outputs</B>
(SSOs), we can limit the number of I/O drivers that can be attached to any
one VDD and GND pad, and we can design the output buffer to limit the slew
rate of the output (we call these slew-rate limited I/O pads). <B>Quiet-I/O</B>
cells also use two separate power supplies and two sets of I/O drivers:
an AC supply (clean or quiet supply) with small AC drivers for the I/O circuits
that start and stop the output slewing at the beginning and end of a output
transition, and a DC supply (noisy or dirty supply) for the transistors
that handle large currents as they slew the output.</P>
<P><P CLASS="Body"><A NAME="pgfId=110759"></A>The three-state buffer allows
us to employ the same pad for input and output<B> bidirectional I/O</B>
. When we want to use the pad as an input, we set OE low and take the data
from DATAin. Of course, it is not necessary to have all these features on
every pad: We can build output-only or input-only pads.</P>
<P><TABLE BORDER="0" CELLSPACING="2" CELLPADDING="0">
<TR>
<TD><P CLASS="TableFigTitleSide"><A NAME="pgfId=110764"></A>FIGURE 2.33 A
three-state bidirectional output buffer. When the output enable, OE, is
'1' the output section is enabled and drives the I/O pad. When OE is '0'
the output buffer is placed in a high-impedance state.</TD>
<TD><P><P CLASS="TableFigure"><A NAME="pgfId=110769"></A> </P>
<P><IMG SRC="CH02-114.gif" WIDTH="221" HEIGHT="162" NATURALSIZEFLAG="3"
ALIGN="BOTTOM"></TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=110770"></A>We can also use many of these
output cell features for input cells that have to drive large on-chip loads
(a clock pad cell, for example). Some gate arrays simply turn an output
buffer around to drive a grid of interconnect that supplies a clock signal
internally. With a typical interconnect capacitance of 0.2
<SPAN CLASS="White"> </SPAN>pFcm<SUP CLASS="Superscript">
–1</SUP> , a grid of 100<SPAN CLASS="White"> </SPAN>cm
(consisting of 10 by 10 lines running all the way across a 1<SPAN CLASS="White"> </SPAN>cm
chip) presents a load of 20<SPAN CLASS="White"> </SPAN>pF
to the clock buffer.</P>
<P><P CLASS="Body"><A NAME="pgfId=110775"></A>Some libraries include I/O
cells that have passive pull-ups or pull-downs (resistors) instead of the
transistors, M1 and M2 (the resistors are normally still constructed from
transistors with long gate lengths). We can also omit one of the driver
transistors, M1 or M2, to form <B>open-drain</B> outputs that require an
external pull-up or pull-down. We can design the output driver to produce
TTL output levels rather than CMOS logic levels. We may also add input hysteresis
(using a Schmitt trigger) to the input buffer, I1 in Figure 2.33, to
accept input data signals that contain glitches (from bouncing switch contacts,
for example) or that are slow rising. The input buffer can also include
a <B>level shifter</B> to accept TTL input levels and shift the input signal
to CMOS levels.</P>
<P><P CLASS="Body"><A NAME="pgfId=110785"></A>The gate oxide in CMOS transistors
is extremely thin (100<SPAN CLASS="White"> </SPAN>Å
or less). This leaves the gate oxide of the I/O cell input transistors susceptible
to breakdown from static electricity (<B> electrostatic discharge</B> ,
or <B>ESD</B> ). ESD arises when we or machines handle the package leads
(like the shock I sometimes get when I touch a doorknob after walking across
the carpet at work). Sometimes this problem is called <B>electrical overstress</B>
(EOS) since most ESD-related failures are caused not by gate-oxide breakdown,
but by the thermal stress (melting) that occurs when the <SPAN CLASS="EmphasisPrefix">
n</SPAN> -channel transistor in an output driver overheats (melts) due to
the large current that can flow in the drain diffusion connected to a pad
during an ESD event.</P>
<P><P CLASS="Body"><A NAME="pgfId=110796"></A>To protect the I/O cells from
ESD, the input pads are normally tied to device structures that clamp the
input voltage to below the gate breakdown voltage (which can be as low as
10<SPAN CLASS="White"> </SPAN>V with a 100<SPAN CLASS="White"> </SPAN>Å
gate oxide). Some I/O cells use transistors with a special <B>ESD implant</B>
that increases breakdown voltage and provides protection. I/O driver transistors
can also use elongated drain structures (ladder structures) and large drain-to-gate
spacing to help limit current, but in a salicide process that lowers the
drain resistance this is difficult. One solution is to mask the I/O cells
during the salicide step. Another solution is to use <SPAN CLASS="EmphasisPrefix">
pnpn</SPAN> and <SPAN CLASS="EmphasisPrefix"> npnp</SPAN> diffusion structures
called silicon-controlled rectifiers (SCRs) to clamp voltages and divert
current to protect the I/O circuits from ESD.</P>
<P><P CLASS="Body"><A NAME="pgfId=110802"></A>There are several ways to
model the capability of an I/O cell to withstand EOS. The <B>human-body
model</B> (<B> HBM</B> ) represents ESD by a 100<SPAN CLASS="White"> </SPAN>pF
capacitor discharging through a 1.5<SPAN CLASS="White"> </SPAN>k<SPAN CLASS="Symbol">W</SPAN>
resistor (this is an International Electrotechnical Committee,
IEC, specification). Typical voltages generated by the human body are in
the range of 24<SPAN CLASS="White"> </SPAN>kV,
and we often see an I/O pad cell rated by the voltage it can withstand using
the HBM. The <B>machine model</B> (<B> MM</B> ) represents an ESD event
generated by automated machine handlers. Typical MM parameters use a 200<SPAN CLASS="White"> </SPAN>pF
capacitor (typically charged to 200<SPAN CLASS="White"> </SPAN>V)
discharged through a 25<SPAN CLASS="White"> </SPAN><SPAN CLASS="Symbol">W</SPAN>
resistor,<SPAN CLASS="Symbol"> </SPAN> corresponding to a peak
initial current of nearly 10<SPAN CLASS="White"> </SPAN>A.
The <B>charge-device model</B> (<B> CDM</B> , also called device chargedischarge)
represents the problem when an IC package is charged, in a shipping tube
for example, and then grounded. If the maximum charge on a package is 3<SPAN CLASS="White"> </SPAN>nC
(a typical measured figure) and the package capacitance to ground is 1.5<SPAN CLASS="White"> </SPAN>pF,
we can simulate this event by charging a 1.5<SPAN CLASS="White"> </SPAN>pF
capacitor to 2<SPAN CLASS="White"> </SPAN>kV
and discharging it through a 1<SPAN CLASS="White"> </SPAN><SPAN CLASS="Symbol">W</SPAN>
resistor.</P>
<P><P CLASS="Body"><A NAME="pgfId=110816"></A>If the diffusion structures
in the I/O cells are not designed with care, it is possible to construct
an SCR structure unwittingly, and instead of protecting the transistors
the SCR can enter a mode where it is latched on and conducting large enough
currents to destroy the chip. This failure mode is called <B>latch-up</B>
. Latch-up can occur if the <SPAN CLASS="EmphasisPrefix"> pn</SPAN> -diodes
on a chip become forward-biased and inject minority carriers (electrons
in <SPAN CLASS="EmphasisPrefix"> p</SPAN> -type material, holes in <SPAN CLASS="EmphasisPrefix">
n</SPAN> -type material) into the substrate. The sourcesubstrate and drainsubstrate
diodes can become forward-biased due to power-supply bounce or output <B>undershoot</B>
(the cell outputs fall below <SPAN CLASS="EquationVariables">V</SPAN><SUB CLASS="SubscriptVariable">SS</SUB> )
or <B>overshoot</B> (outputs rise to greater than <SPAN CLASS="EquationVariables">
V</SPAN><SUB CLASS="SubscriptVariable">DD</SUB> ) for example. These injected
minority carriers can travel fairly large distances and interact with nearby
transistors causing latch-up. I/O cells normally surround the I/O transistors
with <B>guard rings</B> (a continuous ring of <SPAN CLASS="EmphasisPrefix">
n</SPAN> -diffusion in an <SPAN CLASS="EmphasisPrefix">n</SPAN>-well connected
to VDD, and a ring of <SPAN CLASS="EmphasisPrefix">p</SPAN>-diffusion
in a <SPAN CLASS="EmphasisPrefix">p</SPAN>-well connected to VSS) to collect
these minority carriers. This is a problem that can also occur in the logic
core and this is one reason that we normally include substrate and well
connections to the power supplies in every cell.</P>
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