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<H2>2.5 Sequential Logic Cells</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=38939"></A>There are two main
approaches to clocking in VLSI design: <B>multiphase clocks</B> or a single
clock and <B>synchronous design</B> . The second approach has the following
key advantages: (1) it allows automated design, (2) it is safe,
and (3) it permits vendor signoff (a guarantee that the ASIC will work as
simulated). These advantages of synchronous design (especially the last
one) usually outweigh every other consideration in the choice of a clocking
scheme. The vast majority of ASICs use a rigid synchronous design style.</P>
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