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<H2>2.12 References</H2>
<P><P CLASS="Reference"><A NAME="pgfId=202456"></A>Page numbers in brackets
after a reference indicate its location in the chapter body.</P>
<P><P CLASS="Reference"><A NAME="pgfId=163032"></A>Bedrij, O. 1962. "Carry
select adder." IRE Transactions on Electronic Computers, vol. 11, pp.
340346. Original reference to carry-select adder. See also [Weste, 1993]
p. 532. [p. 84]</P>
<P><P CLASS="Reference"><A NAME="pgfId=169194"></A>Booth, A. 1951. "A
signed binary multiplication technique." Quarterly Journal of Mechanics
and Applied Mathematics, vol. 4, pt. 2, pp. 236240. Original reference for
the Booth-encoded multiplier. See also Swartzlander [1990] and Weste [1993,
pp. 547554]. [p. 91]</P>
<P><P CLASS="Reference"><A NAME="pgfId=169186"></A>Brent, R., and H. T.
Kung. 1982. "A regular layout for parallel adders." IEEE Transactions
on Computers, vol. 31, no. 3, pp. 260264. Describes a regular carry-lookahead
adder. [p. 84]</P>
<P><P CLASS="Reference"><A NAME="pgfId=192580"></A>Brodersen, R. (Ed.).
1992. <SPAN CLASS="Emphasis"> Anatomy of a Silicon Compiler.</SPAN> Boston:
Kluwer, 362 p. ISBN 0-7923-9249-3. TK7874.A59.</P>
<P><P CLASS="Reference"><A NAME="pgfId=179499"></A>Campbell, S. 1996. <SPAN CLASS="Emphasis">
The Science and Engineering of Microelectronic Fabrication.</SPAN> New York:
Oxford University Press, 536 p. ISBN 0-19-510508-7. TK7871.85.C25. [p. 116]</P>
<P><P CLASS="Reference"><A NAME="pgfId=192546"></A>Cavanagh, J. J. F. 1984.
<SPAN CLASS="Emphasis"> Digital Computer Arithmetic Design and Implementation.</SPAN>
New York: McGraw-Hill, 468 p. QA76.9.C62.C38. ISBN 0070102821.</P>
<P><P CLASS="Reference"><A NAME="pgfId=192591"></A>Chandrakasan A. P., and
R. Brodersen. 1995. <SPAN CLASS="Emphasis"> Low Power Digital CMOS Design.</SPAN>
Boston: Kluwer, 424 p. ISBN 0-7923-9576-X. TK7871.99.M44C43.</P>
<P><P CLASS="Reference"><A NAME="pgfId=192472"></A>Chang, C. Y., and S.
M. Sze. 1996. <SPAN CLASS="Emphasis"> ULSI Technology.</SPAN> New York:
McGraw-Hill, 726 p. ISBN 0070630623.</P>
<P><P CLASS="Reference"><A NAME="pgfId=165163"></A>Chen, C. H. (Ed.). 1992.
<SPAN CLASS="Emphasis"> Computer Engineering Handbook.</SPAN> New York:
McGraw-Hill. ISBN 0-07-010924-9. TK7888.3.C652. Chapter 4, "Computer
arithmetic," by E. E. Swartzlander, pp. 20, contains descriptions of
adder, multiplier, and divider architectures.</P>
<P><P CLASS="Reference"><A NAME="pgfId=181512"></A>Chen, J. Y. 1990. CMOS
Devices and Technology for VLSI. Englewood Cliffs, NJ: Prentice-Hall, 348
p. ISBN 0-13-138082-6. TK7874.C523.</P>
<P><P CLASS="Reference"><A NAME="pgfId=153443"></A>Dadda, L. 1965. "Some
schemes for parallel multipliers." Alta Frequenza, vol. 34, pp. 349356.
The original reference to the Dadda multiplier. This paper contains some
errors in the diagrams for the multipliers; some remain in the reprint in
Swartzlander [1990, vol. 1]. See also sequel papers: L. Dadda and D. Ferrari,
"Digital multipliers: a unified approach," Alta Frequenza, vol.
37, pp. 10791086, 1968; and L. Dadda, "On parallel digital multipliers,"
Alta Frequenza, vol. 45, pp. 574580, 1976. [p. 92]</P>
<P><P CLASS="Reference"><A NAME="pgfId=180606"></A>Denyer, P. B., and D.
Renshaw. 1985. <SPAN CLASS="Emphasis"> VLSI Signal Processing: A Bit-Serial
Approach.</SPAN> Reading, MA: Addison-Wesley, 312 p. ISBN 0201144042. TK7874.D46.
See also P. B. Denyer and S. G. Smith, <SPAN CLASS="Emphasis"> Serial-Data
Computation.</SPAN> Boston: Kluwer, 1988, 239 p. ISBN 089838253X. TK7874.S623.
[p. 88]</P>
<P><P CLASS="Reference"><A NAME="pgfId=165462"></A>Diaz, C. H., <SPAN CLASS="Emphasis">
et al.</SPAN> 1995. Modeling of Electrical Overstress in Integrated Circuits.
Norwell, MA: Kluwer Academic, 148 p. ISBN 0-7923-9505-0. TK7874.D498. Includes
101 references. Introduction to ESD problems and models.</P>
<P><P CLASS="Reference"><A NAME="pgfId=7935"></A>Ferrari, D., and R. Stefanelli.
1969. "Some new schemes for parallel multipliers." Alta Frequenza,
vol. 38, pp. 843852. The original reference for the FerrariStefanelli multiplier.
Describes the use of 2-bit and 3-bit submultipliers to generate the product
array. Contains tables showing the number of stages and delay for different
configurations. [p. 93]</P>
<P><P CLASS="Reference"><A NAME="pgfId=192507"></A>Gajski, D. D. (Ed.).
1988. <SPAN CLASS="Emphasis"> Silicon Compilation.</SPAN> Reading, MA: Addison-Wesley,
450 p. ISBN 0-201-109915-2. TK7874.S52.</P>
<P><P CLASS="Reference"><A NAME="pgfId=202454"></A>Goldberg, D. 1990. "Computer
arithmetic." In D. A. Patterson and J. L. Hennessy, <SPAN CLASS="Emphasis">
Computer Architecture: A Quantitative Approach.</SPAN> San Mateo, CA: Morgan
Kaufmann, 2nd ed., 1995. QA76.9.A73. P377. ISBN 1-55860-329-8. See also
the first edition of this book (1990).</P>
<P><P CLASS="Reference"><A NAME="pgfId=192220"></A>Haskard, M. R., and I.
C. May. 1988. Analog VLSI Design: nMOS and CMOS. Englewood Cliffs, NJ: Prentice-Hall,
243 p. ISBN 0-13-032640-2. TK7874.H392.</P>
<P><P CLASS="Reference"><A NAME="pgfId=192513"></A>Hwang, K. 1979. <SPAN CLASS="Emphasis">
Computer Arithmetic: Principles, Architecture, and Design.</SPAN> New York:
Wiley, 423 p. ISBN 0471034967. TK7888.3.H9.</P>
<P><P CLASS="Reference"><A NAME="pgfId=192636"></A>Katz, R. H., 1994. <SPAN CLASS="Emphasis">
Contemporary Logic Design.</SPAN> Reading, MA: Addison-Wesley, 699 p. ISBN
0-8053-2703-7.</P>
<P><P CLASS="Reference"><A NAME="pgfId=153389"></A>Keutzer, K., S. Malik,
and A. Saldanha. 1991. "Is redundancy necessary to reduce delay?"
IEEE Transactions on Computer-Aided Design, vol. 10, no. 4, pp. 427435.
Describes the carry-skip adder. The paper describes the redundant logic
that is added in a carry-skip adder and how to remove it without changing
the function or delay of the circuit. [p. 83]</P>
<P><P CLASS="Reference"><A NAME="pgfId=165391"></A>Lehman, M., and N. Burla.
1961. "Skip techniques for high-speed carry-propagation in binary arithmetic
units." IRE Transactions on Electronic Computers, vol. 10, pp. 691698.
Original reference to carry-skip adder. [p. 83]</P>
<P><P CLASS="Reference"><A NAME="pgfId=192410"></A>MacSorley, O. L. 1961.
"High speed arithmetic in binary computers." IRE Proceedings,
vol. 49, pp. 6791. Early reference to carry-lookahead adder. Reprinted in
Swartzlander [1990, vol. 1]. See also Weste [1993, pp. 526529]. [p. 84]</P>
<P><P CLASS="Reference"><A NAME="pgfId=200597"></A>Mead, C. A. 1989. <SPAN CLASS="Emphasis">
Analog VLSI and Neural Systems.</SPAN> Reading, MA: Addison-Wesley, p.371.
ISBN 0-201-05992-4. QA76.5.M39. Includes a description of MOS device operation.</P>
<P><P CLASS="Reference"><A NAME="pgfId=192415"></A>Muller, R. S., and T.
I. Kamins. 1977. <SPAN CLASS="Emphasis"> Device Electronics for Integrated
Circuits.</SPAN> New York: Wiley, p. 404. ISBN 0-471-62364-4. TK7871.85.M86.
See also the second edition of this book (1986).</P>
<P><P CLASS="Reference"><A NAME="pgfId=165127"></A>Mukherjee, A. 1986. Introduction
to nMOS and CMOS VLSI Systems Design. Englewood Cliffs, NJ: Prentice-Hall,
370 p. ISBN 0-13-490947-X. TK7874.M86.</P>
<P><P CLASS="Reference"><A NAME="pgfId=7964"></A>Rabaey, J. 1996. <SPAN CLASS="Emphasis">
Digital Integrated Circuits: A Design Perspective.</SPAN> Englewood Cliffs,
NJ: Prentice-Hall, pp. 700. ISBN 0-13-178609-1. TK7874.65.R33. Chapters
4 and 7 describe the design of full-custom CMOS datapath circuits.</P>
<P><P CLASS="Reference"><A NAME="pgfId=190112"></A>Ranganathan, N. (Ed.).
1993. <SPAN CLASS="Emphasis"> VLSI Algorithms and Architectures: Fundamentals.</SPAN>
New York: IEEE Press, 305 p. ISBN 0-8186-4390-0. TK7874.V5554. See also
N. Ranganathan (Ed.), 1993. <SPAN CLASS="Emphasis"> VLSI Algorithms and
Architectures: Advanced Concepts.</SPAN> New York: IEEE Press, 303 p.
ISBN 0-8186-4400-1. TK7874.V555. Collections of articles mostly from <SPAN CLASS="Emphasis">
Computer</SPAN> and <SPAN CLASS="Emphasis"> IEEE Transactions on Computers</SPAN>
.</P>
<P><P CLASS="Reference"><A NAME="pgfId=181736"></A>Sato, T., <SPAN CLASS="Emphasis">
et al</SPAN> . 1992. "An 8.5<SPAN CLASS="White"> </SPAN>ns
112-b transmission gate adder with a conflict-free bypass circuit."
IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 657659. Describes
an implementation of a carry-bypass adder. [p. 82]</P>
<P><P CLASS="Reference"><A NAME="pgfId=195948"></A>Sklansky, J. 1960. "Conditional-sum
addition logic." IRE Transactions on Electronic Computers, vol. 9,
pp. 226231. Original reference to conditional-sum adder. Several texts have
propagated an error in the spelling of Sklansky (two k's). See also [Weste,
1993] pp. 532533; A. Rothermel <SPAN CLASS="Emphasis"> et al</SPAN> ., "Realization
of transmission-gate conditional-sum (TGCS) adders with low latency time,"
IEEE Journal of Solid-State Circuits, vol. 24, no. 3, 1989, pp. 558561;
each of these are examples of adders based on Sklansky's design. [p. 86]</P>
<P><P CLASS="Reference"><A NAME="pgfId=195953"></A>Swartzlander, E. E.,
Jr. 1990. <SPAN CLASS="Emphasis"> Computer Arithmetic.</SPAN> Los Alamitos,
CA: IEEE Computer Society Press, vols. 1 and 2. ISBN 0818689315 (vol. 1).
QA76.6.C633. Volume 1 is a reprint (originally published: Stroudsberg, PA:
Dowden, Hutchinson & Ross). Volume 2 is a sequel. Contains reprints
of many of the early (19601970) journal articles on adder and multiplier
architectures.</P>
<P><P CLASS="Reference"><A NAME="pgfId=165479"></A>Sze, S. (Ed.). 1988.
<SPAN CLASS="Emphasis"> VLSI Technology.</SPAN> New York: McGraw-Hill, 676
p. ISBN 0-07-062735-5. TK7874.V566. Edited book on fabrication technology.</P>
<P><P CLASS="Reference"><A NAME="pgfId=179510"></A>Trontelj, J., et al.
1989. Analog Digital ASIC Design. New York: McGraw-Hill, 249 p. ISBN 0-07-707300-2.
TK7874.T76.</P>
<P><P CLASS="Reference"><A NAME="pgfId=7952"></A>Uyemura, J. P. 1992. Circuit
Design for CMOS VLSI. Boston: Kluwer, 450 p. ISBN 0-7923-9184-5. TK7874.U93.
See also: J. P. Uyemura, 1988, Fundamentals of MOS Digital Integrated Circuits,
Reading, MA: Addison-Wesley, 624 p. ISBN 0-201-13318-0. TK7874.U94. Includes
basic circuit equations related to NMOS and CMOS logic design.</P>
<P><P CLASS="Reference"><A NAME="pgfId=180605"></A>Wakerly, J. F. 1994.
Digital Design: Principles and Practices. 2nd ed. Englewood Cliffs, NJ:
Prentice-Hall, 840 p. ISBN 0-13-211459-3. TK7874.65.W34. Undergraduate level
introduction to logic design covering: binary arithmetic, CMOS and TTL,
combinational logic, PLDs, sequential logic, memory, and the IEEE standard
logic symbols.</P>
<P><P CLASS="Reference"><A NAME="pgfId=192498"></A>Wallace, C. S. 1960.
"A suggestion for a fast multiplier." IEEE Transactions on Electronic
Computers, vol. 13, pp. 1417. Original reference to Wallace-tree multiplier.
Reprinted in Swartzlander [1990, vol. 1]. [p. 91]</P>
<P><P CLASS="Reference"><A NAME="pgfId=192491"></A>Waser, S., and M. J.
Flynn. 1982. <SPAN CLASS="Emphasis"> Introduction to Arithmetic for Digital
Systems Designers.</SPAN> New York: Holt, Rinehart, and Winston, 308 p.
ISBN 0030605717. TK7895.A65.W37. [p. 116]</P>
<P><P CLASS="Reference"><A NAME="pgfId=106221"></A>Weste, N. H. E., and
K. Eshraghian. 1993. Principles of CMOS VLSI Design: A Systems Perspective.
2nd ed. Reading, MA: Addison-Wesley, 713 p. ISBN 0-201-53376-6. TK7874.W46.
Chapter 5 covers CMOS logic gate design. Chapter 8 covers datapath elements.
See also the first edition of this book. [p. 82]</P>
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