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<DIV>
<H1 CLASS="ChapterTitle">
<A NAME="pgfId=286">
</A>
<BR>
CMOS LOGIC</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=106686">
</A>
A <SPAN CLASS="Definition">
CMOS transistor</SPAN>
(or device) has four terminals: <SPAN CLASS="Definition">
gate</SPAN>
, <SPAN CLASS="Definition">
source</SPAN>
, <SPAN CLASS="Definition">
drain</SPAN>
, and a fourth terminal that we shall ignore until the next section. A CMOS transistor is a switch. The switch must be conducting or <SPAN CLASS="Emphasis">
on</SPAN>
to allow current to flow between the source and drain terminals (using open and closed for switches is confusing—for the same reason we say a tap is <SPAN CLASS="Emphasis">
on</SPAN>
and not that it is <SPAN CLASS="Emphasis">
closed</SPAN>
). The transistor source and drain terminals are equivalent as far as digital signals are concerned—we do not worry about labeling an electrical switch with two terminals. </P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=142633">
</A>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
AB</SUB>
is the potential difference, or voltage, between nodes A and B in a circuit; <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
AB</SUB>
is positive if node A is more positive than node B.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=142635">
</A>
Italics denote variables; constants are set in roman (upright) type. Uppercase letters denote DC, large-signal, or steady-state voltages.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=142673">
</A>
For TTL the positive power supply is called VCC (V<SUB CLASS="Subscript">
CC</SUB>
or <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
CC</SUB>
). The 'C' denotes that the supply is connected indirectly to the collectors of the <SPAN CLASS="EmphasisPrefix">
npn</SPAN>
bipolar transistors (a bipolar transistor has a collector, base, and emitter—corresponding roughly to the drain, gate, and source of an MOS transistor).</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=142677">
</A>
Following the example of TTL we used VDD (V<SUB CLASS="Subscript">
DD </SUB>
or <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
) to denote the positive supply in an NMOS chip where the devices are all <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistors and the drains of these devices are connected indirectly to the positive supply. The supply nomenclature for NMOS chips has stuck for CMOS.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=165767">
</A>
VDD is the name of the power supply node or net; <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
represents the value (uppercase since <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
is a DC quantity). Since <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
is a variable, it is italic (words and multiletter abbreviations use roman—thus it is <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
, but <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
drain</SUB>
).</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=142648">
</A>
Logic designers often call the CMOS negative supply VSS or <SPAN CLASS="EquationVariables">
VSS</SPAN>
even if it is actually ground or GND. I shall use VSS for the node and <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SS</SUB>
for the value.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=122200">
</A>
CMOS uses <SPAN CLASS="Definition">
positive logic</SPAN>
—VDD is logic '1' and VSS is logic '0'. </LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=72866">
</A>
We turn a transistor on or off using the gate terminal. There are two kinds of CMOS transistors: <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistors and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistors. An <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor requires a logic '1' (from now on I’ll just say a '1') on the gate to make the switch conducting (to turn the transistor <SPAN CLASS="Emphasis">
on</SPAN>
). A <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor requires a logic '0' (again from now on, I’ll just say a '0') on the gate to make the switch nonconducting (to turn the transistor <SPAN CLASS="Emphasis">
off</SPAN>
). The <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor symbol has a bubble on its gate to remind us that the gate has to be a '0' to turn the transistor <SPAN CLASS="Emphasis">
on</SPAN>
. All this is shown in Figure 2.1(a) and (b). </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=105447">
</A>
</P>
<DIV>
<IMG SRC="CH02-1.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=105459">
</A>
FIGURE 2.1 CMOS transistors as switches. (a) An <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor. (b) A <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor. (c) A CMOS inverter and its symbol (an <SPAN CLASS="Emphasis">
equilateral</SPAN>
triangle and a <SPAN CLASS="Emphasis">
circle</SPAN>
).</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=8620">
</A>
If we connect an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor in series with a <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor, as shown in Figure 2.1(c), we form an <SPAN CLASS="Definition">
inverter</SPAN>
. With four transistors we can form a two-input <SPAN CLASS="Definition">
NAND gate</SPAN>
(Figure 2.2a). We can also make a two-input <SPAN CLASS="Definition">
NOR gate</SPAN>
(Figure 2.2b). Logic designers normally use the terms NAND gate and logic gate (or just gate), but I shall try to use the terms NAND <SPAN CLASS="Definition">
cell</SPAN>
and<SPAN CLASS="Definition">
logic cell</SPAN>
rather than NAND gate or logic gate in this chapter to avoid any possible confusion with the gate terminal of a transistor.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=214713">
</A>
<IMG SRC="CH02-2.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=105491">
</A>
FIGURE 2.2 CMOS logic. (a) A two-input NAND logic cell. (b) A two-input NOR logic cell. The <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor switches implement the '1's and '0's of a Karnaugh map.</P>
</TD>
</TR>
</TABLE>
</DIV>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.1.htm#pgfId=8524" CLASS="Hypertext">
2.1 CMOS Transistors</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.2.htm#pgfId=41692" CLASS="Hypertext">
2.2 The CMOS Process</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.3.htm#pgfId=5065" CLASS="Hypertext">
2.3 CMOS Design Rules</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.4.htm#pgfId=799" CLASS="Hypertext">
2.4 Combinational Logic Cells</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.5.htm#pgfId=38934" CLASS="Hypertext">
2.5 Sequential Logic Cells</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.6.htm#pgfId=83860" CLASS="Hypertext">
2.6 Datapath Logic Cells</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.7.htm#pgfId=110715" CLASS="Hypertext">
2.7 I/O Cells</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.8.htm#pgfId=83872" CLASS="Hypertext">
2.8 Cell Compilers</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.9.htm#pgfId=147420" CLASS="Hypertext">
2.9 Summary</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.a.htm#pgfId=88389" CLASS="Hypertext">
2.10 Problems</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.b.htm#pgfId=194312" CLASS="Hypertext">
2.11 Bibliography</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH02.c.htm#pgfId=163031" CLASS="Hypertext">
2.12 References</A>
</H1>
<HR><P>[ <A HREF="../../ASICs.htm#anchor749424">Chapter Index</A> ] [ <A HREF="CH02.1.htm">Next page</A> ]</P></BODY>
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