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</A>
2.8 (Stipple patterns, 30 min.) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=215125">
</A>
a. Check the stipple patterns in Figure 2.9. Using ruled paper draw 8-by-8 stipple patterns for all the combinations of layers shown. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215126">
</A>
b. Repeat part a for Figure 2.10.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=72719">
</A>
2.9 (Select, 20 min.) Can you draw a design-rule correct (according to the design rules in Tables 2.7–2.9) layout with a piece of select that has a minimum width of 2 <SPAN CLASS="Symbol">
l</SPAN>
(rule 4.4)?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=54836">
</A>
2.10 (*Inverter layout, 60 min.) Using 1/4-inch ruled paper (or similar) draw a minimum-size inverter (W/L = 1 for both <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel and <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistors). Use a scale of one square to 2 <SPAN CLASS="Symbol">
l</SPAN>
and the design rules in Table 2.7–Table 2.9. Do not use m2 or m3—only m1. Draw the nwell, pwell, ndiff, and pdiff layers, but not the implant layers or the active layer. Include connections to the input, output, VDD, and VSS in m1. There must be at least one well connection to each well (<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-well to VDD, and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-well to VSS). Minimize the size of your cell BB. Draw the BB outline and write its size in <SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
on your drawing. Use green diagonal stripes for ndiff, brown diagonal stripes for pdiff, red diagonal stripes for poly, blue diagonal stripes for m1, solid black for contact). Include a key on your drawing, and clearly label the input, output, VDD, and VSS contacts.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=153256">
</A>
2.11 (*AOI221 Layout, 120 min.) Layout the AOI221 shown in Figure 2.13 with the design rules of Tables 2.7–2.9 and using Figure 1.3 as a guide. Label clearly the m1 corresponding to the inputs, output, VDD bus, and GND (VSS) bus. Remember to include substrate contacts. What is the size of your BB in <SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=16020">
</A>
2.12 (Resistance, 20 min.) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=215129">
</A>
a. Using the values for sheet resistance shown in Table 2.3, calculate the resistance of a 200 <SPAN CLASS="Symbol">
l</SPAN>
long (in the direction of current flow) by 3<SPAN CLASS="Symbol">
l</SPAN>
wide piece of each of the layers. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215130">
</A>
b. Estimate the resistance of an 8-inch, 10 <SPAN CLASS="Symbol">
W </SPAN>
cm, <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type, <100> wafer, measured (i) from edge to edge across a diameter and (ii) from face center to the face center on the other side.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=131440">
</A>
2.13 (*Layout graphics, 120 min.) Write a tutorial for capturing layout. As an example:</P>
<P CLASS="Exercise">
<A NAME="pgfId=137096">
</A>
To capture EPSF (encapsulated PostScript format) from Tanner Research’s L-Edit for documentation, Macintosh version... Create a black-and-white technology file, use Setup, Layers..., in L-Edit. The method described here does not work well for grayscale or color. Use File, Print..., Destination check button File to print from L-Edit to an EPS (encapsulated PostScript) file. After you choose Save, a dialog box appears. Select Format: EPS Enhanced Mac Preview, ASCII, Level 1 Compatible, Font Inclusion: None. Save the file. Switch to Frame. Create an Anchored Frame. Use File, Import, File... to bring up a dialog box. Check button Copy into Document, select Format: EPSF. Import the EPS file that will appear as a “page image”. Grab the graphic inside the Anchored Frame and move the “page image” around. There will be a footer with text on the “page image” that you may want to hide by using the Anchored Frame edges to crop the image.</P>
<P CLASS="Exercise">
<A NAME="pgfId=137103">
</A>
Your instructions should be precise, concise, assume nothing, and use the names of menu items, buttons and so on exactly as they appear to the user. Most of the layout figures in this book were created using L-Edit running on a Macintosh, with labels added in FrameMaker. Most of the layouts use the Compass layout editor. </P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=106162">
</A>
2.14 (Transistor resistance, 20 min.) Calculate <SPAN CLASS="EquationVariables">
I</SPAN>
<SUB CLASS="Subscript">
DS</SUB>
and the resistance (the DC value <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
/<SPAN CLASS="EquationVariables">
I</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
as well as the AC value ∂<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
/<SPAN CLASS="EquationVariables">
∂I</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
as appropriate) of long-channel transistors with the following parameters, under the specified conditions. In each case state whether the transistor is in the saturation region, linear region, or off: </P>
<P CLASS="Exercise">
<A NAME="pgfId=106171">
</A>
<SPAN CLASS="Bold">
(i)</SPAN>
<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel: <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
t</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
= 0.5 V, <SPAN CLASS="Symbol">
b</SPAN>
<SUB CLASS="SubscriptVariable">
n</SUB>
= 40 <SPAN CLASS="Symbol">
m</SPAN>
AV<SUP CLASS="Superscript">
–2</SUP>
:</P>
<P CLASS="Exercise">
<A NAME="pgfId=106165">
</A>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
= 3.3V: <SPAN CLASS="Bold">
a.</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
= 3.3 V <SPAN CLASS="Bold">
b.</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
= 0.0 V <SPAN CLASS="Bold">
c.</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
= 0.0 V, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
= 3.3 V</P>
<P CLASS="Exercise">
<A NAME="pgfId=106167">
</A>
<SPAN CLASS="Bold">
(ii)</SPAN>
<SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel: <SPAN CLASS="EquationNumber">
V</SPAN>
<SUB CLASS="Subscript">
t</SUB>
<SUB CLASS="SubscriptVariable">
p</SUB>
= –0.6 V, <SPAN CLASS="Symbol">
b</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
= 20 <SPAN CLASS="Symbol">
m</SPAN>
AV<SUP CLASS="Superscript">
–2</SUP>
: </P>
<P CLASS="Exercise">
<A NAME="pgfId=106168">
</A>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
= 0.0 V: <SPAN CLASS="Bold">
a.</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
= 0.0 V <SPAN CLASS="Bold">
b. </SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
= –5.0 V <SPAN CLASS="Bold">
c.</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
= –5.0 V, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
= –5.0 V </P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=200687">
</A>
2.15 (Circuit theory, 15 min.) You accidentally created the “inverter” shown in Figure 2.35 on a full-custom ASIC currently being fabricated. Will it work? Your manager wants a yes or no answer. Your group is a little more understanding: You are to make a presentation to them to explain the problems ahead. Prepare two foils as well as a one page list of alternatives and recommendations.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigTitleSide">
<A NAME="pgfId=200699">
</A>
FIGURE 2.34 A CMOS “inverter” with <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistors swapped (Problem 2.15).</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=200704">
</A>
</P>
<DIV>
<IMG SRC="CH02-46.gif">
</DIV>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseHead">
<A NAME="pgfId=200705">
</A>
2.16 (Mask resolution, 10 min.) People use LaserWriters to make printed-circuit boards all the time. </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=215136">
</A>
a. Do you think it is possible to make an IC mask using a 600 dpi (dots per inch) LaserWriter and a transparency? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215137">
</A>
b. What would <SPAN CLASS="Symbol">
l</SPAN>
be? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215138">
</A>
c. (Harder) See if you can use a microscope to look at the dot and the rectangular bars (serifs) of a letter 'i' from the output of a LaserWriter on paper (most are 300 dpi or 600 dpi). Estimate <SPAN CLASS="Symbol">
l</SPAN>
. What is causing the problem? Why is there no rush to generate 1200 dpi LaserWriters for paper? Put a page of this textbook under the microscope: can you see the difference? What are the similar problems printing patterns on a wafer?</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=179747">
</A>
2.17 (Lambda, 10 min.) Estimate <SPAN CLASS="Symbol">
l</SPAN>
</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=215139">
</A>
a. for your TV screen, </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215140">
</A>
b. for your computer monitor, </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215141">
</A>
c. (harder) a photograph.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=107095">
</A>
2.18 (Pass-transistor logic, 10 min.) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=215143">
</A>
a. In Figure 2.36 suppose we set A = B = C = D = '1', what is the value of F? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215144">
</A>
b. What is the logic strength of the signal at F? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215145">
</A>
c. If <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
= 5 V and <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
t</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
= 0.6 V, what would the voltage at the source and drain terminals of M1, M2, and M3 be? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215146">
</A>
d. Will this circuit still work if <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
= 3 V? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215142">
</A>
e. At what point does it stop working? </LI>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigTitleSide">
<A NAME="pgfId=107102">
</A>
FIGURE 2.35 </P>
<P CLASS="TableFigTitleSide">
<A NAME="pgfId=215382">
</A>
FIGURE 2.36 A pass transistor chain (Problem 2.18).</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=107110">
</A>
<IMG SRC="CH02-47.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
</TABLE>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=107202">
</A>
2.19 (Transistor parameters, 20 min.) Calculate the <SPAN CLASS="Bold">
(a)</SPAN>
electron and <SPAN CLASS="Bold">
(b)</SPAN>
hole mobility for the transistor parameters given in Section 2.1 if k<SUP CLASS="Superscript">
'</SUP>
<SUB CLASS="SubscriptVariable">
n</SUB>
= 80 <SPAN CLASS="Symbol">
mA</SPAN>
V<SUP CLASS="Superscript">
–2</SUP>
and k<SUP CLASS="Superscript">
'</SUP>
<SUB CLASS="SubscriptVariable">
p</SUB>
= 40 <SPAN CLASS="Symbol">
mA</SPAN>
V<SUP CLASS="Superscript">
–2</SUP>
. </P>
<P CLASS="Exercise">
<A NAME="pgfId=190307">
</A>
Answer: (a) 0.023 m<SUP CLASS="Superscript">
2</SUP>
V<SUP CLASS="Superscript">
–1</SUP>
s<SUP CLASS="Superscript">
–1</SUP>
.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=107221">
</A>
2.20 (Quantum behavior, 10 min.) The average thermal energy of an electron is approximately <SPAN CLASS="EquationNumber">
kT</SPAN>
, where <SPAN CLASS="EquationNumber">
k</SPAN>
= 1.38 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–23</SUP>
JK<SUP CLASS="Superscript">
–1</SUP>
is Boltzmann’s constant and T is the absolute temperature in kelvin.</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=307840">
</A>
a. The kinetic energy of an electron is (1/2)<SPAN CLASS="EquationNumber">
m</SPAN>
<SPAN CLASS="EquationVariables">
v</SPAN>
<SUP CLASS="Superscript">
2</SUP>
, where <SPAN CLASS="EquationVariables">
v</SPAN>
is due to random thermal motion, and <SPAN CLASS="EquationNumber">
m</SPAN>
= 9.11 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–31</SUP>
kg is the rest mass. What is <SPAN CLASS="EquationVariables">
v</SPAN>
at 300 K?</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=307852">
</A>
b. The electron wavelength <SPAN CLASS="EquationVariables">
l</SPAN>
= <SPAN CLASS="EquationNumber">
h</SPAN>
/<SPAN CLASS="EquationVariables">
p</SPAN>
, where <SPAN CLASS="EquationNumber">
h</SPAN>
= 6.62 <SPAN CLASS="Symbol">
¥</SPAN>
10–34 Js is the Planck constant, and <SPAN CLASS="EquationVariables">
p</SPAN>
= <SPAN CLASS="EquationNumber">
m</SPAN>
<SPAN CLASS="EquationVariables">
v</SPAN>
is the electron momentum. What is <SPAN CLASS="EquationVariables">
l</SPAN>
at 25<SPAN CLASS="Symbol">
∞</SPAN>
C?</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=122582">
</A>
c. Compare the thermal velocity with the saturation velocity.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=122583">
</A>
d. Compare the electron wavelength with the MOS channel length and with the gate-oxide thickness in a 0.25 <SPAN CLASS="Symbol">
m</SPAN>
m process and a 0.1 <SPAN CLASS="Symbol">
m</SPAN>
m process.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=30480">
</A>
2.21 (Gallium arsenide, 5 min.) The electron mobility in GaAs is about 8500 cm<SUP CLASS="Superscript">
2</SUP>
V<SUP CLASS="Superscript">
–1</SUP>
s<SUP CLASS="Superscript">
–1</SUP>
; the hole mobility is about 400 cm<SUP CLASS="Superscript">
2</SUP>
V<SUP CLASS="Superscript">
–1</SUP>
s<SUP CLASS="Superscript">
–1</SUP>
. If we could make complementary <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel GaAs transistors (the same way that we do in a CMOS process) what would the ratio of a GaAs inverter be to equalize rise and fall times? About how much faster would you expect GaAs transistors to be than silicon for the same transistor sizes?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=147163">
</A>
2.22 (Margaret of Anjou, 5 min.) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=215149">
</A>
a. Why is it ones’ complement but two’s complement? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215150">
</A>
b. Why Queen’s University, Belfast but Queens’ College, Cambridge?</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=143289">
</A>
2.23 (Logic cell equations, 5 min.) Show that Eq. 2.31, 2.36, and 2.37 are correct.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=143404">
</A>
2.24 (Carry-lookahead equations, 10 min.) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=215151">
</A>
a. Derive the carry-lookahead equations for <SPAN CLASS="EquationVariables">
i</SPAN>
= 8. Write them in the same form as Eq. 2.56. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215152">
</A>
b. Derive the equations for the Brent–Kung structure for <SPAN CLASS="EquationVariables">
i</SPAN>
= 8.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=40795">
</A>
2.25 (OAI cells, 20 min.) Draw a circuit schematic, including transistor sizes, for <SPAN CLASS="Bold">
(a)</SPAN>
an OAI321 cell, <SPAN CLASS="Bold">
(b)</SPAN>
an AOI321 cell. <SPAN CLASS="Bold">
(c)</SPAN>
Which do you think will be larger?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=107530">
</A>
2.26 (**Making stipple patterns) Construct a set of black-and-white, transparent, 8-by-8 stipple patterns for a CMOS process in which we draw both well layers, the active layer, poly, and both diffusion implant layers separately. Consider only the layers up to m1 (but include m1 and the contact layer). One useful tool is the Apple Macintosh Control Panel, 'General Controls,' that changes the Mac desktop pattern.</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=122578">
</A>
a. (60 min.) Create a set of patterns with which you can detect any errors (for example, <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-well and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-well overlap, or <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-implant and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-implant overlap). </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=122579">
</A>
b. (60 min.+) Using a layout of an inverter as an example, find a set of patterns that allows you to trace transistors and connections (a very qualitative goal).</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=123116">
</A>
c. (Days+) Find a set of grayscale stipple patterns that allow you to produce layouts that “look nice” in a report (much, much harder than it sounds).</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=16014">
</A>
2.27 (AOI and OAI cells, 10 min.). Draw the circuit schematics for an AOI22 and an OAI22 cell. Clearly label each transistor as on or off for each cell for an input vector of (A1, A2, B1, B2) = (0101).</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=136792">
</A>
2.28 (Flip-flops and latches, 10 min.) In no more than 20 words describe the difference between a flip-flop and a latch.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=177680">
</A>
2.29 (**An old argument) Should setup and hold times appear under maximum, minimum, or typical in a data sheet? (From Peter Alfke.)</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=177674">
</A>
2.30 (***Setup, 20 min.) “There is no such thing as a setup and hold time, just two setup times—for a '1' and for a '0'.” Comment. (From Clemenz Portmann.)</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=300213">
</A>
2.31 (Subtracter, 20 min.) Show that you can rewrite the equations for a full subtract⌨️ 快捷键说明
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