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<H1 CLASS="Heading1">
<A NAME="pgfId=88389">
</A>
2.10 Problems</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=8671">
</A>
* = Difficult,** = Very difficult, *** = Extremely difficult</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=137163">
</A>
2.1 (Switches, 20 min.) <SPAN CLASS="Bold">
(a)</SPAN>
Draw a circuit schematic for a two-way light switch: flipping the switch at the top or bottom of the stairs reverses the state of two light bulbs, one at the top and one at the bottom of the stairs. Your schematic should show and label all the cables, switches, and bulbs. <SPAN CLASS="Bold">
(b)</SPAN>
Repeat the problem for three switches and one light in a warehouse.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=179261">
</A>
2.2 (Logic, 10 min.) The queen wished to choose her successor wisely. She blindfolded and then placed a crown on each of her three children, explaining that there were three red and two blue crowns, and they must deduce the color of their own crown. With blindfolds removed the children could see the two other crowns, but not their own. After a while Anne said: “My crown is red.” How did she know?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=105701">
</A>
2.3 (Minus signs, 20 min.) The channel charge in an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor is negative. <SPAN CLASS="Bold">
(a)</SPAN>
Should there not be a minus sign in Eq. 2.5 to account for this? <SPAN CLASS="Bold">
(b)</SPAN>
If so, then where in the derivation of Section 2.1 does the minus sign disappear to arrive at Eq. 2.9 for the current in an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor? <SPAN CLASS="Bold">
(c)</SPAN>
The equations for the current in a <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor (Eq. 2.15) have the opposite sign to those for an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor. Where in the derivation in Section 2.1 does the extra minus sign arise?</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigTitleSide">
<A NAME="pgfId=215328">
</A>
FIGURE 2.33 Transistor characteristics for a 0.3 <SPAN CLASS="Symbol">
m</SPAN>
m process (Problem 2.4).</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=215336">
</A>
<IMG SRC="CH02-45.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseHead">
<A NAME="pgfId=162048">
</A>
2.4 (Transistor curves, 20 min.) Figure 2.34 shows the measured <SPAN CLASS="EquationVariables">
I</SPAN>
<SUB CLASS="Subscript">
DS</SUB>
–<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
characteristics for a 20/20 <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor in a 0.3 <SPAN CLASS="Symbol">
m</SPAN>
m (effective gate length) process from an ASIC foundry. Derive as much information as you can from this figure.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=8700">
</A>
2.5 (Body effect, 20 min). The equations for the drain–source current (2.9, 2.12, and 2.15) do not contain <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SB</SUB>
, the source voltage with respect to the bulk, because we assumed that it was zero. This is not true for the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor whose drain is connected to the output in a two-input NAND gate, for example. A reverse <SPAN CLASS="Definition">
substrate bias</SPAN>
(or back-gate bias; <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SB</SUB>
> 0 for an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor) makes the bulk act like a second gate (the back gate) and modifies an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor threshold voltage as follows: </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=382610">
</A>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
tn</SUB>
= V<SUB CLASS="Subscript">
t0</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
+ <SPAN CLASS="Symbol">
g</SPAN>
[ √(<SPAN CLASS="Symbol">
f</SPAN>
<SUB CLASS="Subscript">
0</SUB>
+ <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SB</SUB>
) – √<SPAN CLASS="Symbol">
f</SPAN>
<SUB CLASS="Subscript">
0 </SUB>
] ,</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=382612">
</A>
(2.67)</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=181828">
</A>
where <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
t</SUB>
<SUB CLASS="Subscript">
0</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
is measured with <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SB</SUB>
= 0 V; <SPAN CLASS="Symbol">
f</SPAN>
<SUB CLASS="Subscript">
0</SUB>
is called the surface potential; and <SPAN CLASS="Symbol">
g</SPAN>
(gamma) is the <SPAN CLASS="Definition">
body-effect coefficient</SPAN>
(back-gate bias coefficient), </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=382655">
</A>
<SPAN CLASS="Symbol">
g</SPAN>
= √(2q<SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
Si</SUB>
N<SUB CLASS="Subscript">
A</SUB>
)/C<SUB CLASS="Subscript">
ox</SUB>
.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=382657">
</A>
(2.68)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Exercise">
<A NAME="pgfId=190194">
</A>
There are several alternative names and symbols for <SPAN CLASS="Symbol">
f</SPAN>
<SUB CLASS="Subscript">
0</SUB>
(“phi,” a positive quantity for an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor, typically between 0.6–0.7 V)—you may also see <SPAN CLASS="Symbol">
f</SPAN>
<SUB CLASS="SubscriptVariable">
b</SUB>
(for bulk potential) or 2<SPAN CLASS="Symbol">
f</SPAN>
<SUB CLASS="Subscript">
F</SUB>
(twice the Fermi potential, a negative quantity). In Eq. 2.68, <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
Si</SUB>
= <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
0</SUB>
<SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
r</SUB>
= 1.053 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–10</SUP>
Fm<SUP CLASS="Superscript">
–1</SUP>
is the <SPAN CLASS="Definition">
permittivity of silicon</SPAN>
(the permittivity of a vacuum <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
0</SUB>
= 8.85 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–12</SUP>
Fm<SUP CLASS="Superscript">
–1</SUP>
and the relative permittivity of silicon is <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
r</SUB>
= 11.7); <SPAN CLASS="EquationNumber">
N</SPAN>
<SUB CLASS="Subscript">
A</SUB>
is the acceptor doping concentration in the bulk (for <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type substrate or well—<SPAN CLASS="EquationNumber">
N</SPAN>
<SUB CLASS="Subscript">
D</SUB>
for the donor concentration in an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-type substrate or well); and <SPAN CLASS="EquationNumber">
C</SPAN>
<SUB CLASS="Subscript">
ox</SUB>
is the gate capacitance per unit area given by </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=382672">
</A>
C<SUB CLASS="Subscript">
ox</SUB>
= <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
ox</SUB>
/T<SUB CLASS="Subscript">
ox</SUB>
.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=382674">
</A>
(2.69)</P>
</TD>
</TR>
</TABLE>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=202561">
</A>
a. Calculate the theoretical value of <SPAN CLASS="Symbol">
g</SPAN>
for <SPAN CLASS="EquationNumber">
N</SPAN>
<SUB CLASS="Subscript">
A</SUB>
= 10<SUP CLASS="Superscript">
16</SUP>
cm<SUP CLASS="Superscript">
–3</SUP>
, <SPAN CLASS="EquationNumber">
T</SPAN>
<SUB CLASS="Subscript">
ox</SUB>
= 100 Å.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215097">
</A>
b. Calculate and plot <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
t</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
for <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SB</SUB>
ranging from 0 V to 5 V in increments of 1 V assuming values of <SPAN CLASS="Symbol">
g</SPAN>
= 0.5 V<SUP CLASS="Superscript">
0.5</SUP>
, <SPAN CLASS="Symbol">
f</SPAN>
<SUB CLASS="Subscript">
0</SUB>
= 0.6 V, and <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
t0</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
= 0.5 V obtained from transistor characteristics.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215102">
</A>
c. Fit a linear approximation to <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
t</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215103">
</A>
d. Recognizing <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SB</SUB>
<SPAN CLASS="Symbol">
£</SPAN>
0 V, rewrite Eq. 2.67 for a <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel device. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215104">
</A>
e. (Harder) What effect does the back-gate bias effect have on CMOS logic circuits?</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=183181">
</A>
Answer: (a) 0.17 V<SUP CLASS="Superscript">
0.5</SUP>
(b) 0.50 – 1.3 V.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=181811">
</A>
2.6 (Sizing layout, 10 min.) Stating clearly whatever assumptions you make and describing the tools and methods you use, estimate the size (in <SPAN CLASS="Symbol">
l</SPAN>
) of the standard cell shown in Figure 1.3. Estimate the size of each of the transistors, giving their channel lengths and widths (stating clearly which is which).</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=167279">
</A>
2.7 (CMOS process) (20 min.) Table 2.15 shows the major steps involved in a typical deep submicron CMOS process. There are approximately 100 major steps in the process. </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=215105">
</A>
a. If each major step has a yield of 0.9, what is the overall process yield? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215106">
</A>
b. If the process yield is 90 % (not uncommon), what is the average yield at each major step? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215107">
</A>
c. If each of the major steps in Table 2.15 consists of an average of five other microtasks, what is the average yield of each of the 500 microtasks. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215111">
</A>
d. Suppose, for example, an operator loads and unloads a furnace five times a day as a microtask, how many days must the operator work without making a mistake to achieve this microtask yield? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215112">
</A>
e. Does this seem reasonable? What is wrong with our model?</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=215113">
</A>
f. (**60 min.) Draw the process cross-section showing, in particular, the poly, FOX, gate oxide, IMOs and metal layers. You may have to make some assumptions about the meanings and functions of the various steps and layers. Assume all layers are deposited on top of each other according to the thicknesses shown (do not attempt to correct for the silicon consumed during oxidation—even if you understand what this means). The abbreviations in Table 2.15 are as follows: dep. = deposition; LPCVD = low-pressure chemical vapor deposition (for growing oxide and poly); LDD = lightly doped drain (a way to improve transistor characteristics); SOG = silicon overglass (a deposited quartz to help with step coverage between metal layers).</LI>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="9">
<P CLASS="TableTitle">
<A NAME="pgfId=169545">
</A>
TABLE 2.15 CMOS process steps (Problem 2.7).<A HREF="#pgfId=202524" CLASS="footnote">
1</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=169563">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=169565">
</A>
<SPAN CLASS="TableHeads">
Step</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=169567">
</A>
<SPAN CLASS="TableHeads">
Depth</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=169569">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=169571">
</A>
<SPAN CLASS="TableHeads">
Step</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=169573">
</A>
<SPAN CLASS="TableHeads">
Depth</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=169575">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=169577">
</A>
<SPAN CLASS="TableHeads">
Step</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=169579">
</A>
<SPAN CLASS="TableHeads">
Depth</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=169581">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=169583">
</A>
substrate</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=169585">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=169587">
</A>
32</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=169589">
</A>
resist strip</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=169591">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=169593">
</A>
63</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=169595">
</A>
m1 mask</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=169597">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=169599">
</A>
2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=169601">
</A>
oxide 1 dep.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=169603">
</A>
500</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=169605">
</A>
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