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1.5 ASIC Cell Libraries</H1>
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The cell library is the key part of ASIC design. For a programmable ASIC the FPGA company supplies you with a library of logic cells in the form of a <SPAN CLASS="Definition">
design kit</SPAN>
, you normally do not have a choice, and the cost is usually a few thousand dollars. For MGAs and CBICs you have three choices: the <SPAN CLASS="Definition">
ASIC vendor</SPAN>
(the company that will build your ASIC) will supply a cell library, or you can buy a cell library from a third-party <SPAN CLASS="Definition">
library vendor</SPAN>
, or you can build your own cell library.</P>
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The first choice, using an <SPAN CLASS="Definition">
ASIC-vendor library</SPAN>
, requires you to use a set of design tools approved by the ASIC vendor to enter and simulate your design. You have to buy the tools, and the cost of the cell library is folded into the NRE. Some ASIC vendors (especially for MGAs) supply tools that they have developed in-house. For some reason the more common model in Japan is to use tools supplied by the ASIC vendor, but in the United States, Europe, and elsewhere designers want to choose their own tools. Perhaps this has to do with the relationship between customer and supplier being a lot closer in Japan than it is elsewhere.</P>
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An ASIC vendor library is normally a <SPAN CLASS="Definition">
phantom library</SPAN>
—the cells are empty boxes, or <SPAN CLASS="Definition">
phantoms</SPAN>
, but contain enough information for layout (for example, you would only see the bounding box or abutment box in a phantom version of the cell in Figure 1.3). After you complete layout you <SPAN CLASS="Definition">
hand off</SPAN>
a netlist to the ASIC vendor, who fills in the empty boxes (<SPAN CLASS="Definition">
phantom instantiation</SPAN>
) before manufacturing your chip.</P>
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The second and third choices require you to make a <SPAN CLASS="Definition">
buy-or-build decision</SPAN>
. If you complete an ASIC design using a cell library that you bought, you also own the masks (the <SPAN CLASS="Definition">
tooling</SPAN>
) that are used to manufacture your ASIC. This is called <SPAN CLASS="Definition">
customer-owned tooling</SPAN>
(<SPAN CLASS="Definition">
COT</SPAN>
, pronounced “see-oh-tee”). A library vendor normally develops a cell library using information about a process supplied by an <SPAN CLASS="Definition">
ASIC foundry</SPAN>
. An ASIC foundry (in contrast to an ASIC vendor) only provides manufacturing, with no design help. If the cell library meets the foundry specifications, we call this a <SPAN CLASS="Definition">
qualified cell library</SPAN>
. These cell libraries are normally expensive (possibly several hundred thousand dollars), but if a library is qualified at several foundries this allows you to shop around for the most attractive terms. This means that buying an expensive library can be cheaper in the long run than the other solutions for high-volume production. </P>
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The third choice is to develop a cell library in-house. Many large computer and electronics companies make this choice. Most of the cell libraries designed today are still developed in-house despite the fact that the process of <SPAN CLASS="Definition">
library development</SPAN>
is complex and very expensive. </P>
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However created, each cell in an ASIC cell library must contain the following:</P>
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A physical layout</LI>
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A behavioral model</LI>
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A Verilog/VHDL model</LI>
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A detailed timing model</LI>
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A test strategy</LI>
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A circuit schematic</LI>
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A cell icon</LI>
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A wire-load model</LI>
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A routing model</LI>
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For MGA and CBIC cell libraries we need to complete cell design and <SPAN CLASS="Definition">
cell layout </SPAN>
and shall discuss this in Chapter 2. The ASIC designer may not actually see the layout if it is hidden inside a phantom, but the layout will be needed eventually. In a programmable ASIC the cell layout is part of the programmable ASIC design (see Chapter 4).</P>
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The ASIC designer needs a high-level, <SPAN CLASS="Definition">
behavioral model</SPAN>
for each cell because simulation at the detailed timing level takes too long for a complete ASIC design. For a NAND gate a behavioral model is simple. A multiport RAM model can be very complex. We shall discuss behavioral models when we describe Verilog and VHDL in Chapter 10 and Chapter 11. The designer may require Verilog and VHDL models in addition to the models for a particular logic simulator.</P>
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ASIC designers also need a detailed <SPAN CLASS="Definition">
timing model</SPAN>
for each cell to determine the performance of the critical pieces of an ASIC. It is too difficult, too time-consuming, and too expensive to build every cell in silicon and measure the cell delays. Instead library engineers simulate the delay of each cell, a process known as <SPAN CLASS="Definition">
characterization</SPAN>
. Characterizing a standard-cell or gate-array library involves <SPAN CLASS="Definition">
circuit extraction</SPAN>
from the full-custom cell layout for each cell. The extracted schematic includes all the parasitic resistance and capacitance elements. Then library engineers perform a simulation of each cell including the parasitic elements to determine the switching delays. The simulation models for the transistors are derived from measurements on special chips included on a wafer called <SPAN CLASS="Definition">
process control monitors</SPAN>
(<SPAN CLASS="Definition">
PCMs</SPAN>
) or <SPAN CLASS="Definition">
drop-ins</SPAN>
. Library engineers then use the results of the circuit simulation to generate detailed timing models for logic simulation. We shall cover timing models in Chapter 13.</P>
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All ASICs need to be production tested (programmable ASICs may be tested by the manufacturer before they are customized, but they still need to be tested). Simple cells in small or medium-size blocks can be tested using automated techniques, but large blocks such as RAM or multipliers need a planned strategy. We shall discuss test in Chapter 14.</P>
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The <SPAN CLASS="Definition">
cell schematic</SPAN>
(a netlist description) describes each cell so that the cell designer can perform simulation for complex cells. You may not need the detailed cell schematic for all cells, but you need enough information to compare what you think is on the silicon (the schematic) with what is actually on the silicon (the layout)—this is a <SPAN CLASS="Definition">
layout versus schematic</SPAN>
(<SPAN CLASS="Definition">
LVS</SPAN>
) check.</P>
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If the ASIC designer uses schematic entry, each cell needs a <SPAN CLASS="Definition">
cell icon</SPAN>
together with connector and naming information that can be used by design tools from different vendors. We shall cover ASIC design using schematic entry in Chapter 9. One of the advantages of using <SPAN CLASS="Definition">
logic synthesis</SPAN>
(Chapter 12) rather than schematic design entry is eliminating the problems with icons, connectors, and cell names. Logic synthesis also makes moving an ASIC between different cell libraries, or <SPAN CLASS="Definition">
retargeting</SPAN>
, much easier.</P>
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In order to estimate the parasitic capacitance of wires before we actually complete any routing, we need a statistical estimate of the capacitance for a net in a given size circuit block. This usually takes the form of a look-up table known as a <SPAN CLASS="Definition">
wire-load model</SPAN>
. We also need a <SPAN CLASS="Definition">
routing model</SPAN>
for each cell. Large cells are too complex for the physical design or layout tools to handle directly and we need a simpler representation—a <SPAN CLASS="Definition">
phantom</SPAN>
—of the physical layout that still contains all the necessary information. The phantom may include information that tells the automated routing tool where it can and cannot place wires over the cell, as well as the location and types of the connections to the cell. </P>
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