ch01.4.htm

介绍asci设计的一本书

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FIGURE&nbsp;1.13&nbsp; A profit model. If a product is introduced on time, the total sales are $60&nbsp;million (the area of the higher triangle). With a three-month (one fiscal quarter) delay the sales decline to $25&nbsp;million. The difference is shown as the shaded area between the two triangles and amounts to a lost revenue of $35&nbsp;million.</P>
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Suppose we have the following situation:</P>
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The product lifetime is 18 months (6 fiscal quarters).</LI>
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The product sales increase (linearly) at $10&nbsp;million per quarter independently of when the product is introduced (we suppose this is because we can increase production and sales only at a fixed rate).</LI>
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The product reaches its peak sales at a point in time that is independent of when we introduce a product (because of external market factors that we cannot control).</LI>
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The product declines in sales (linearly) to the end of its life&#8212;a point in time that is also independent of when we introduce the product (again due to external market forces).</LI>
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The simple profit and revenue model of Figure&nbsp;1.13 shows us that we would lose $35&nbsp;million in sales in this situation due to a 3-month delay. Despite the obvious problems with such a simple model (how can we introduce the same product twice to compare the performance?), it is widely used in marketing. In the electronics industry product lifetimes continue to shrink. In the PC industry it is not unusual to have a product lifetime of 18 months or less. This means that it is critical to achieve a rapid design time (or high <SPAN CLASS="Definition">
product velocity</SPAN>
) with no delays.</P>
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The last fixed cost shown in Figure&nbsp;1.12 corresponds to an &#8220;insurance policy.&#8221; When a company buys an ASIC part, it needs to be assured that it will always have a back-up source, or <SPAN CLASS="Definition">
second source</SPAN>
, in case something happens to its first or primary source. Established FPGA companies have a second source that produces equivalent parts. With a custom ASIC you may have to do some redesign to transfer your ASIC to the second source. However, for all ASIC types, switching production to a second source will involve some cost. Figure&nbsp;1.12 assumes a second-source cost of $2000 for all types of ASIC (the amount may be substantially more than this). </P>
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1.4.4&nbsp;ASIC Variable Costs</H2>
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Figure&nbsp;1.14 shows a spreadsheet, &#8220;Variable Costs,&#8221; that calculates some example part costs. This spreadsheet uses the terms and parameters defined below the figure. </P>
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FIGURE&nbsp;1.14&nbsp;A spreadsheet, &#8220;Variable Costs,&#8221; to calculate the part cost (that is the variable cost for a product using ASICs) for different ASIC technologies.</P>
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The <SPAN CLASS="Definition">
wafer size </SPAN>
increases every few years. From 1985 to 1990, 4-inch to 6-inch diameter wafers were common; equipment using 6-inch to 8-inch wafers was introduced between 1990 and 1995; the next step is the 300 cm or 12-inch wafer. The 12-inch wafer will probably take us to 2005.</LI>
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The <SPAN CLASS="Definition">
wafer cost</SPAN>
 depends on the equipment costs, process costs, and overhead in the fabrication line. A typical wafer cost is between $1000 and $5000, with $2000 being average; the cost declines slightly during the life of a process and increases only slightly from one process generation to the next.</LI>
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<SPAN CLASS="Definition">
Moore&#8217;s Law</SPAN>
 (after Gordon Moore of Intel) models the observation that the number of transistors on a chip roughly doubles every 18 months. Not all designs follow this law, but a &#8220;large&#8221; ASIC design seems to grow by a factor of 10 every 5 years (close to Moore&#8217;s Law). In 1990 a large ASIC design size was 10 k-gate, in 1995 a large design was about 100 k-gate, in 2000 it will be 1 M-gate, in 2005 it will be 10 M-gate. </LI>
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The <SPAN CLASS="Definition">
gate density</SPAN>
 is the number of gate equivalents per unit area (remember: a gate equivalent, or gate, corresponds to a two-input NAND gate). </LI>
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The <SPAN CLASS="Definition">
gate utilization</SPAN>
 is the percentage of gates that are on a die that we can use (on a gate array we waste some gate space for interconnect).</LI>
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The <SPAN CLASS="Definition">
die size</SPAN>
 is determined by the design size (in gates), the gate density, and the utilization of the die.</LI>
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The number of <SPAN CLASS="Definition">
die per wafer</SPAN>
 depends on the die size and the wafer size (we have to pack rectangular or square die, together with some test chips, on to a circular wafer so some space is wasted).</LI>
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The <SPAN CLASS="Definition">
defect density</SPAN>
 is a measure of the quality of the fabrication process. The smaller the defect density the less likely there is to be a flaw on any one die. A single defect on a die is almost always fatal for that die. Defect density usually increases with the number of steps in a process. A defect density of less than 1 cm<SUP CLASS="Superscript">
&#8211;2</SUP>
 is typical and required for a submicron CMOS process.</LI>
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The <SPAN CLASS="Definition">
yield</SPAN>
 of a process is the key to a profitable ASIC company. The yield is the fraction of die on a wafer that are good (expressed as a percentage). Yield depends on the complexity and maturity of a process. A process may start out with a yield of close to zero for complex chips, which then climbs to above 50 percent within the first few months of production. Within a year the yield has to be brought to around 80 percent for the average complexity ASIC for the process to be profitable. Yields of 90 percent or more are not uncommon.</LI>
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The <SPAN CLASS="Definition">
die cost</SPAN>
 is determined by wafer cost, number of die per wafer, and the yield. Of these parameters, the most variable and the most critical to control is the yield.</LI>
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The <SPAN CLASS="Definition">
profit margin</SPAN>
 (what you sell a product for, less what it costs you to make it, divided by the cost) is determined by the ASIC company&#8217;s fixed and variable costs. ASIC vendors that make and sell custom ASICs have huge fixed and variable costs associated with building and running fabrication facilities (a fabrication plant is a <SPAN CLASS="Definition">
fab</SPAN>
). FPGA companies are typically <SPAN CLASS="Definition">
fabless</SPAN>
&#8212;they do not own a fab&#8212;they must pass on the costs of the chip manufacture (plus the profit margin of the chip manufacturer) and the development cost of the FPGA structure in the FPGA part cost. The profitability of any company in the ASIC business varies greatly.</LI>
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The <SPAN CLASS="Definition">
price per gate</SPAN>
 (usually measured in cents per gate) is determined by die costs and design size. It varies with design size and declines over time.</LI>
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The <SPAN CLASS="Definition">
part cost</SPAN>
 is determined by all of the preceding factors. As such it will vary widely with time, process, yield, economic climate, ASIC size and complexity, and many other factors.</LI>
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As an estimate you can assume that the price per gate for any process technology falls at about 20 % per year during its life (the average life of a CMOS process is 2&#8211;4 years, and can vary widely). Beyond the life of a process, prices can increase as demand falls and the fabrication equipment becomes harder to maintain. Figure&nbsp;1.15 shows the price per gate for the different ASICs and process technologies using the following assumptions:</P>
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For any new process technology the price per gate decreases by 40 % in the first year, 30 % in the second year, and then remains constant.</LI>
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A new process technology is introduced approximately every 2 years, with feature size decreasing by a factor of two every 5 years as follows: 2 <SPAN CLASS="Symbol">
m</SPAN>
m in 1985, 1.5 <SPAN CLASS="Symbol">
m</SPAN>
m in 1987, 1 <SPAN CLASS="Symbol">
m</SPAN>
m in 1989, 0.8&#8211;0.6 <SPAN CLASS="Symbol">
m</SPAN>
m in 1991&#8211;1993, 0.5&#8211;0.35 <SPAN CLASS="Symbol">
m</SPAN>
m in 1996&#8211;1997, 0.25&#8211;0.18 <SPAN CLASS="Symbol">
m</SPAN>
m in 1998&#8211;2000.</LI>
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CBICs and MGAs are introduced at approximately the same time and price.</LI>
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The price of a new process technology is initially 10 % above the process that it replaces.</LI>
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FPGAs are introduced one year after CBICs that use the same process technology.</LI>
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The initial FPGA price (per gate) is 10 percent higher than the initial price for CBICs or MGAs using the same process technology.</LI>
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From Figure&nbsp;1.15 you can see that the successive introduction of new process technologies every 2 years drives the price per gate down at a rate close to 30 percent per year. The cost figures that we have used in this section are very approximate and can vary widely (this means they may be off by a factor of 2 but probably are correct within a factor of 10). ASIC companies do use spreadsheet models like these to calculate their costs. </P>
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FIGURE&nbsp;1.15&nbsp;Example price per gate figures. </P>
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Having decided if, and then which, ASIC technology is appropriate, you need to choose the appropriate cell library. Next we shall discuss the issues surrounding ASIC cell libraries: the different types, their sources, and their contents.</P>
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