📄 ch13.2.htm
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<P CLASS="EquationNumbered">
<A NAME="pgfId=59372">
</A>
<SPAN CLASS="BodyComputer">
tI0Z (IO->Z) = 0.90 + 0.07 + (1.76 </SPAN>
<A NAME="14196">
</A>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="BodyComputer">
Cld) ns</SPAN>
(13.1)</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=59373">
</A>
The capacitance, <SPAN CLASS="BodyComputer">
Cld</SPAN>
, at the output of each MUX is zero (because nothing is connected to the outputs). From Eq. <A HREF="CH13.2.htm#17024" CLASS="XRef">
13.1</A>
, the path delay from the input, <SPAN CLASS="BodyComputer">
a[0]</SPAN>
, to the output, <SPAN CLASS="BodyComputer">
outp[0]</SPAN>
, is thus 0.97 ns. This explains why the output, <SPAN CLASS="BodyComputer">
outp[0]</SPAN>
, changes from <SPAN CLASS="BodyComputer">
'0'</SPAN>
to <SPAN CLASS="BodyComputer">
'1'</SPAN>
at <SPAN CLASS="EquationVariables">
t</SPAN>
= 10.97 ns, 0.97 ns after a change occurs on <SPAN CLASS="BodyComputer">
a[0]</SPAN>
. </P>
<P CLASS="Body">
<A NAME="pgfId=80147">
</A>
The gate-level simulation predicts that the input, <SPAN CLASS="BodyComputer">
a[0]</SPAN>
, to the MUX will change before the changes on the inputs have time to propagate to the MUX select. Finally, at <SPAN CLASS="EquationVariables">
t</SPAN>
= 14.15 ns, the MUX select will change and switch the output, <SPAN CLASS="BodyComputer">
outp[0]</SPAN>
, back to <SPAN CLASS="BodyComputer">
'0'</SPAN>
again. The total delay for this input vector stimulus is thus 4.15 ns. Even though this path is a false path (as far as timing analysis is concerned), it is a critical path. It is indeed necessary to wait for 4.15 ns before using the output signal of this circuit. A timing analyzer can only offer us a guarantee that there is no other path that is slower than the critical path.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=62920">
</A>
13.2.4 Net Capacitance</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=62921">
</A>
The timing analyzer predicted a critical path delay of 4.06 ns compared to the gate-level simulation prediction of 4.15 ns. We can check our results by using another gate-level simulator (<A NAME="marker=85162">
</A>
QSim) which uses a slightly different algorithm. Here is the output (with the same input vectors as before):</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=59131">
</A>
@nodes</P>
<P CLASS="Computer">
<A NAME="pgfId=59132">
</A>
a R10 W1; a[2] a[1] a[0]</P>
<P CLASS="Computer">
<A NAME="pgfId=59133">
</A>
b R10 W1; b[2] b[1] b[0]</P>
<P CLASS="Computer">
<A NAME="pgfId=59134">
</A>
outp R10 W1; outp[2] outp[1] outp[0]</P>
<P CLASS="Computer">
<A NAME="pgfId=59135">
</A>
@data</P>
<P CLASS="Computer">
<A NAME="pgfId=59136">
</A>
.00 a -> 'D6</P>
<P CLASS="Computer">
<A NAME="pgfId=59137">
</A>
.00 b -> 'D7</P>
<P CLASS="Computer">
<A NAME="pgfId=59138">
</A>
.00 outp -> 'Du</P>
<P CLASS="Computer">
<A NAME="pgfId=59139">
</A>
.53 outp -> 'Du</P>
<P CLASS="Computer">
<A NAME="pgfId=59140">
</A>
.93 outp -> 'Du</P>
<P CLASS="Computer">
<A NAME="pgfId=59141">
</A>
4.42 outp -> 'D6</P>
<P CLASS="Computer">
<A NAME="pgfId=59142">
</A>
10.00 a -> 'D7</P>
<P CLASS="Computer">
<A NAME="pgfId=59143">
</A>
10.00 b -> 'D6</P>
<P CLASS="Computer">
<A NAME="pgfId=59144">
</A>
11.03 outp -> 'D7</P>
<P CLASS="Computer">
<A NAME="pgfId=59145">
</A>
14.43 outp -> 'D6</P>
<P CLASS="Computer">
<A NAME="pgfId=59146">
</A>
### END OF SIMULATION TIME = 20 ns</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=59147">
</A>
@end</P>
<P CLASS="Body">
<A NAME="pgfId=59148">
</A>
The output is similar but gives yet another value, 4.43 ns, for the path delay. Can this be explained? The simulator prints the following messages as a clue: </P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=59167">
</A>
defCapacitance = .1E-01 pF</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=59165">
</A>
incCapacitance = .1E-01 pF/pin</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=62957">
</A>
The simulator is adding capacitance to the outputs of each of the logic cells to model the parasitic <SPAN CLASS="Definition">
net capacitance</SPAN>
<A NAME="marker=81034">
</A>
(<A NAME="marker=81035">
</A>
interconnect capacitance or <A NAME="marker=81128">
</A>
wire capacitance) that will be present in the physical layout. The simulator adds 0.01 pF (<SPAN CLASS="BodyComputer">
defCapacitance</SPAN>
) on each node and another 0.01 pF (<SPAN CLASS="BodyComputer">
incCapacitance</SPAN>
) for each pin (logic cell input) attached to a node. The model that predicts these values is known as a <SPAN CLASS="Definition">
wire-load model</SPAN>
<A NAME="marker=81036">
</A>
, <SPAN CLASS="Definition">
wire-delay model</SPAN>
<A NAME="marker=81037">
</A>
, or <SPAN CLASS="Definition">
interconnect model</SPAN>
<A NAME="marker=81038">
</A>
. Changing the wire-load model parameters to zero and repeating the simulation changes the critical-path delay to 4.06 ns, which agrees exactly with the logic-synthesizer timing analysis. This emphasizes that the net capacitance may contribute a significant delay. </P>
<P CLASS="Body">
<A NAME="pgfId=81143">
</A>
The library data book (VLSI Technology, vsc450) lists the cell input and output capacitances. For example, the values for the <SPAN CLASS="BodyComputer">
nd02d0</SPAN>
logic cell are as follows: </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=131289">
</A>
<SPAN CLASS="BodyComputer">
Cin (inputs, a1 and a2) = 0.042 pF Cout (output, zn) = 0.038 pF</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=131292">
</A>
(13.2)</P>
</TD>
</TR>
</TABLE>
<P CLASS="EquationNumbered">
<A NAME="pgfId=81144">
</A>
<SPAN CLASS="BodyComputer">
Cin (inputs, a1 and a2) = 0.042 pF Cout (output, zn) = 0.038 pF<BR>
</SPAN>
(13.2)</P>
<P CLASS="Body">
<A NAME="pgfId=80172">
</A>
Armed with this information, let us return to the timing analysis report of <A HREF="CH13.2.htm#23209" CLASS="XRef">
Table 13.1</A>
(the part of this table we shall focus on follows) and examine how a timing analyzer handles net capacitance.</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=63028">
</A>
inPin --> outPin incr arrival trs rampDel cap cell </P>
<P CLASS="Computer">
<A NAME="pgfId=62992">
</A>
(ns) (ns) (ns) (pf) </P>
<P CLASS="Computer">
<A NAME="pgfId=62993">
</A>
---------------------------------------------------------------------</P>
<P CLASS="Computer">
<A NAME="pgfId=66900">
</A>
a[0] .00 .00 R .00 .12 comp_m...</P>
<P CLASS="Computer">
<A NAME="pgfId=66901">
</A>
b1_i3 </P>
<P CLASS="Computer">
<A NAME="pgfId=66902">
</A>
A2 --> ZN .31 .31 F .23 .08 nd02d0 </P>
<P CLASS="ComputerLast">
<A NAME="pgfId=59285">
</A>
...</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=81101">
</A>
The total capacitance at the output node of logic cell instance <SPAN CLASS="BodyComputer">
b1_i3</SPAN>
is 0.08 pF. This figure is the sum of the logic cell (<SPAN CLASS="BodyComputer">
nd02d0</SPAN>
) output capacitance of cell instance <SPAN CLASS="BodyComputer">
b1_i3</SPAN>
(equal to 0.038 pF) and <SPAN CLASS="BodyComputer">
Cld</SPAN>
, the input capacitance of the next cell, <SPAN CLASS="BodyComputer">
b1_i2</SPAN>
(also an <SPAN CLASS="BodyComputer">
nd02d0</SPAN>
), equal to 0.042 pF. </P>
<P CLASS="Body">
<A NAME="pgfId=81114">
</A>
The capacitance at the input node, <SPAN CLASS="BodyComputer">
a[0]</SPAN>
, is equal to the sum of the input capacitances of the logic cells connected to that node. These capacitances (and their sources) are as follows:</P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=81102">
</A>
0.042 pF (the <SPAN CLASS="BodyComputer">
a2</SPAN>
input of the two-input NAND, instance <SPAN CLASS="BodyComputer">
b1_i3</SPAN>
, cell <SPAN CLASS="BodyComputer">
nd02d0)</SPAN>
</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=81103">
</A>
0.038 pF (the <SPAN CLASS="BodyComputer">
i0</SPAN>
input of the 2:1 MUX, instance <SPAN CLASS="BodyComputer">
b1_i1</SPAN>
, cell <SPAN CLASS="BodyComputer">
mx21d1</SPAN>
)</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=81104">
</A>
0.038 pF (the <SPAN CLASS="BodyComputer">
b1</SPAN>
input of the OAI221, instance <SPAN CLASS="BodyComputer">
b1_i2</SPAN>
, cell <SPAN CLASS="BodyComputer">
oa03d1</SPAN>
)</LI>
</OL>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=81105">
</A>
The sum of these capacitances is the 0.12 pF shown in the timing-analysis report. </P>
<P CLASS="Body">
<A NAME="pgfId=65245">
</A>
Having explained the capacitance figures in the timing-analysis report, let us turn to the delay figures. The fall-time delay equation for a <SPAN CLASS="BodyComputer">
nd02d0</SPAN>
logic cell (again from the vsc450 library data book) is as follows: </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=131415">
</A>
<SPAN CLASS="BodyComputer">
tD (AX->ZN) = 0.08 + 0.11 + (2.89 </SPAN>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="BodyComputer">
Cld) ns</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=131417">
</A>
(13.3)</P>
</TD>
</TR>
</TABLE>
<P CLASS="EquationNumbered">
<A NAME="pgfId=65242">
</A>
<SPAN CLASS="BodyComputer">
tD (AX->ZN) = 0.08 + 0.11 + (2.89 </SPAN>
<A NAME="36634">
</A>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="BodyComputer">
Cld) ns</SPAN>
(13.3)</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=66979">
</A>
Notice 0.11 ns = 2.89 nspF–1<SPAN CLASS="Symbol">
¥</SPAN>
0.038 pF, and this figure in Eq. <A HREF="CH13.2.htm#36634" CLASS="XRef">
13.3</A>
is the part of the cell delay attributed to the cell output capacitance. The ramp delay in the timing analysis (under the heading <SPAN CLASS="BodyComputer">
rampDel</SPAN>
in <A HREF="CH13.2.htm#23209" CLASS="XRef">
Table 13.1</A>
) is the sum of the last two terms in Eq. <A HREF="CH13.2.htm#36634" CLASS="XRef">
13.3</A>
. Thus, the ramp delay is 0.11 + (2.89 <SPAN CLASS="Symbol">
¥</SPAN>
0.042 ) = 0.231 ns (since <SPAN CLASS="BodyComputer">
Cld</SPAN>
is 0.042 pF). The total delay (under <SPAN CLASS="BodyComputer">
incr</SPAN>
in <A HREF="CH13.2.htm#23209" CLASS="XRef">
Table 13.1</A>
) is 0.08 + 0.231 = 0.31 ns.</P>
<P CLASS="Body">
<A NAME="pgfId=66980">
</A>
There are thus the following four figures for the critical path delay: </P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=59101">
</A>
4.06 ns from a static timing analysis using the logic-synthesizer timing engine (worst-case process, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
= 4.50 V, and <SPAN CLASS="EquationVariables">
T</SPAN>
= 70<SPAN CLASS="Symbol">
∞</SPAN>
C). No wire capacitance.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=59103">
</A>
4.15 ns from a gate-level functional simulation (worst-case process, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SS</SUB>
= 0.1 V, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
= 4.65 V, and <SPAN CLASS="EquationVariables">
T</SPAN>
= 70<SPAN CLASS="Symbol">
∞</SPAN>
C). No wire capacitance.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=59247">
</A>
4.43 ns from a gate-level functional simulation. Default wire-capacitance model (0.01 pF + 0.01 pF / pin).</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=59245">
</A>
4.06 ns from a gate-level functional simulation. No wire capacitance.</LI>
</OL>
<P CLASS="Body">
<A NAME="pgfId=78155">
</A>
Normally we do not check our simulation results this thoroughly. However, we can only trust the tools if we understand what they are doing, how they work, their limitations, and we are able to check that the results are reasonable. </P>
</DIV>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="TableFootLast">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=85489">
</A>
1Using a 0.8 <SPAN CLASS="Symbol">
m</SPAN>
m standard-cell library, VLSI Technology vsc450. Worst-case environment: worst-case process, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
= 4.75 V, and <SPAN CLASS="EquationVariables">
T</SPAN>
= 70 °C. No wire capacitance, no input or output capacitance, prop–ramp timing model. The structural model was synthesized and optimized using a 0.6 <SPAN CLASS="Symbol">
m</SPAN>
m library, but this timing analysis was performed using the 0.8 <SPAN CLASS="Symbol">
m</SPAN>
m library. This is because the library models are simpler for the 0.8 <SPAN CLASS="Symbol">
m</SPAN>
m library and thus easier to explain in the text.</P>
</DIV>
</DIV>
<HR><P>[ <A HREF="CH13.htm">Chapter start</A> ] [ <A HREF="CH13.1.htm">Previous page</A> ] [ <A HREF="CH13.3.htm">Next page</A> ]</P></BODY>
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