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<TITLE> 13.2 The Comparator/MUX Example</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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13.2 <A NAME="16644">
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The Comparator/MUX Example</H1>
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As an <A NAME="marker=116891">
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example we borrow the model from Section 12.2, “A Comparator/MUX,”</P>
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// comp_mux.v</P>
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<B CLASS="Keyword">
module</B>
comp_mux(a, b, outp); <B CLASS="Keyword">
input</B>
[2:0] a, b; <B CLASS="Keyword">
output</B>
[2:0] outp;</P>
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<B CLASS="Keyword">
function</B>
[2:0] compare; <B CLASS="Keyword">
input</B>
[2:0] ina, inb;</P>
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<B CLASS="Keyword">
begin</B>
<B CLASS="Keyword">
if</B>
(ina <= inb) compare = ina; <B CLASS="Keyword">
else</B>
compare = inb; <B CLASS="Keyword">
end</B>
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<B CLASS="Keyword">
endfunction</B>
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<B CLASS="Keyword">
assign</B>
outp = compare(a, b);</P>
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<B CLASS="Keyword">
endmodule</B>
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We can use the following testbench to generate a sequence of input values (we call these <SPAN CLASS="Definition">
input vectors</SPAN>
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) that test or <SPAN CLASS="Definition">
exercise</SPAN>
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the behavioral model, <SPAN CLASS="BodyComputer">
comp_mux.v</SPAN>
:</P>
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// testbench.v</P>
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<B CLASS="Keyword">
module</B>
comp_mux_testbench;</P>
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<B CLASS="Keyword">
integer</B>
i, j;</P>
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<B CLASS="Keyword">
reg</B>
[2:0] x, y, smaller; <B CLASS="Keyword">
wire</B>
[2:0] z;</P>
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<B CLASS="Keyword">
always</B>
@(x) $display("t x y actual calculated");</P>
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<B CLASS="Keyword">
initial</B>
$monitor("%4g",$time,,x,,y,,z,,,,,,,smaller);</P>
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<B CLASS="Keyword">
initial</B>
$dumpvars; <B CLASS="Keyword">
initial</B>
#1000 $finish; </P>
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</A>
<B CLASS="Keyword">
initial</B>
</P>
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<B CLASS="Keyword">
begin</B>
</P>
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<B CLASS="Keyword">
for</B>
(i = 0; i <= 7; i = i + 1) </P>
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<B CLASS="Keyword">
begin</B>
</P>
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<B CLASS="Keyword">
for</B>
(j = 0; j <= 7; j = j + 1) </P>
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<B CLASS="Keyword">
begin</B>
</P>
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x = i; y = j; smaller = (x <= y) ? x : y; </P>
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#1 if (z != smaller) $display("error");</P>
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<B CLASS="Keyword">
end</B>
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<B CLASS="Keyword">
end</B>
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<B CLASS="Keyword">
end</B>
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comp_mux v_1 (x, y, z);</P>
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<B CLASS="Keyword">
endmodule</B>
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The results from the behavioral simulation are as follows:</P>
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t x y actual calculated</P>
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0 0 0 0 0</P>
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1 0 1 0 0</P>
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... 60 lines omitted...</P>
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62 7 6 6 6</P>
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63 7 7 7 7</P>
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We included a delay of one Verilog time unit in line <A HREF="CH13.2.htm#41922" CLASS="XRef">
15</A>
of the testbench model (allowing time to progress), but we did not specify the units—they could be nanoseconds or days. Thus, behavioral simulation can only tell us if our design does not work; it cannot tell us that real hardware will work.</P>
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13.2.1 <A NAME="23329">
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Structural Simulation</H2>
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We use logic synthesis to produce a structural model from a behavioral model. The following comparator/MUX model is adapted from the example in <A HREF="/Humuhumu/from Antibes/Prof.htm#22485" CLASS="XRef">
Section 12.11</A>
, “<A HREF="/Humuhumu/from Antibes/Prof.htm#22485" CLASS="XRef">
Performance-Driven Synthesis</A>
” (optimized for a 0.6 <SPAN CLASS="Symbol">
m</SPAN>
m standard-cell library):</P>
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`timescale 1ns / 10ps // comp_mux_o2.v</P>
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<B CLASS="Keyword">
module</B>
comp_mux_o (a, b, outp);</P>
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<B CLASS="Keyword">
input</B>
[2:0] a; <B CLASS="Keyword">
input</B>
[2:0] b;</P>
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<B CLASS="Keyword">
output</B>
[2:0] outp;</P>
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<B CLASS="Keyword">
supply1</B>
VDD; <B CLASS="Keyword">
supply0</B>
VSS;</P>
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mx21d1 b1_i1 (.i0(a[0]), .i1(b[0]), .s(b1_i6_zn), .z(outp[0]));</P>
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oa03d1 b1_i2 (.a1(b1_i9_zn), .a2(a[2]), .b1(a[0]), .b2(a[1]),</P>
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.c(b1_i4_zn), .zn(b1_i2_zn));</P>
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nd02d0 b1_i3 (.a1(a[1]), .a2(a[0]), .zn(b1_i3_zn));</P>
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nd02d0 b1_i4 (.a1(b[1]), .a2(b1_i3_zn), .zn(b1_i4_zn));</P>
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mx21d1 b1_i5 (.i0(a[1]), .i1(b[1]), .s(b1_i6_zn), .z(outp[1]));</P>
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oa04d1 b1_i6 (.a1(b[2]), .a2(b1_i7_zn), .b(b1_i2_zn),</P>
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.zn(b1_i6_zn));</P>
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in01d0 b1_i7 (.i(a[2]), .zn(b1_i7_zn));</P>
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an02d1 b1_i8 (.a1(b[2]), .a2(a[2]), .z(outp[2]));</P>
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in01d0 b1_i9 (.i(b[2]), .zn(b1_i9_zn));</P>
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<B CLASS="Keyword">
endmodule</B>
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Logic simulation requires Verilog models for the following six logic cells: <SPAN CLASS="BodyComputer">
mx21d1 </SPAN>
(2:1 MUX), <SPAN CLASS="BodyComputer">
oa03d1</SPAN>
(OAI221), <SPAN CLASS="BodyComputer">
nd02d0</SPAN>
(two-input NAND), <SPAN CLASS="BodyComputer">
oa04d1</SPAN>
(OAI21), <SPAN CLASS="BodyComputer">
in01d0</SPAN>
(inverter), and <SPAN CLASS="BodyComputer">
an02d1</SPAN>
(two-input AND). These models are part of an ASIC library (often encoded so that they cannot be seen) and thus, from this point on, the designer is dependent on a particular ASIC library company. As an example of this dependence, notice that some of the names in the preceding code have changed from uppercase (in Figure 12.8 on p. 624) to lowercase. Verilog is case sensitive and we are using a cell library that uses lowercase. Most unfortunately, there are no standards for names, cell functions, or the use of case in ASIC libraries. </P>
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The following code (a simplified model from a 0.8 <SPAN CLASS="Symbol">
m</SPAN>
m standard-cell library) models a 2:1 MUX and uses fixed delays:</P>
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`timescale 1 ns / 10 ps</P>
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<B CLASS="Keyword">
module</B>
mx21d1 (z, i0, i1, s); <B CLASS="Keyword">
input</B>
i0, i1, s; <B CLASS="Keyword">
output</B>
z;</P>
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<B CLASS="Keyword">
not</B>
G3(N3, s);</P>
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<B CLASS="Keyword">
and</B>
G4(N4, i0, N3), G5(N5, s, i1), G6(N6, i0, i1);</P>
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<B CLASS="Keyword">
or</B>
G7(z, N4, N5, N6);</P>
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<B CLASS="Keyword">
specify</B>
</P>
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<A NAME="23032">
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(i0*>z) = (0.279:0.504:0.900, 0.276:0.498:0.890);</P>
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(i1*>z) = (0.248:0.448:0.800, 0.264:0.476:0.850);</P>
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(s*>z) = (0.285:0.515:0.920, 0.298:0.538:0.960);</P>
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<B CLASS="Keyword">
endspecify</B>
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<B CLASS="Keyword">
endmodule</B>
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This code uses Verilog primitive models (<SPAN CLASS="BodyComputer">
not</SPAN>
, <SPAN CLASS="BodyComputer">
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