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<TITLE> 13.6 Delay Models</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
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<H1 CLASS="Heading1">
<A NAME="pgfId=68436">
</A>
13.6 <A NAME="16413">
</A>
Delay Models</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=68439">
</A>
We shall use the term <A NAME="marker=68453">
</A>
timing model to describe delays outside logic cells and the term <A NAME="marker=68445">
</A>
delay model to describe delays inside logic cells. These terms are not standard and often people use them interchangeably. There are also different terms for various types of delay:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=67550">
</A>
A <A NAME="marker=67549">
</A>
<SPAN CLASS="Definition">
pin-to-pin delay</SPAN>
is a delay between an input pin and an output pin of a logic cell. This usually represents the delay of the logic cell excluding any delay contributed by interconnect.</LI>
<LI CLASS="BulletFirst">
<A NAME="pgfId=68480">
</A>
A <A NAME="marker=68479">
</A>
<SPAN CLASS="Definition">
pin delay</SPAN>
is a delay lumped to a certain pin of a logic cell (usually an input). This usually represents the delay of the interconnect, but may also represent the delay of the logic cell.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=67553">
</A>
A <A NAME="marker=67551">
</A>
<SPAN CLASS="Definition">
net delay</SPAN>
or <A NAME="marker=67552">
</A>
<SPAN CLASS="Definition">
wire delay</SPAN>
is a delay outside a logic cell. This always represents the delay of interconnect.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=125104">
</A>
In this section we shall focus on delay models and logic cell delays. In Chapter 3 we modeled logic cell delay as follows (Eq. 3.10): </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=125108">
</A>
<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PD</SUB>
= <SPAN CLASS="EquationVariables">
R</SPAN>
(<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
out</SUB>
+ <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
) +<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
q</SUB>
<SPAN CLASS="Symbol">
.</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=125111">
</A>
<A NAME="10713">
</A>
(13.5)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=125119">
</A>
<A NAME="38868">
</A>
A linear delay model is also known as a <SPAN CLASS="Definition">
prop–ramp delay model</SPAN>
<A NAME="marker=125118">
</A>
, because the delay comprises a fixed propagation delay (the intrinsic delay) and a ramp delay (the extrinsic delay). As an example, the data book entry for the inverter, cell <SPAN CLASS="BodyComputer">
in01d0</SPAN>
, in a 0.8 <SPAN CLASS="Symbol">
m</SPAN>
m standard-cell library gives the following delay information (with delay measured in nanoseconds and capacitance in picofarads): </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=131462">
</A>
<SPAN CLASS="BodyComputer">
RISE = 0.10 + 0.07 + (1.75 </SPAN>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="BodyComputer">
Cld) FALL = 0.09 + 0.07 + (1.95 </SPAN>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="BodyComputer">
Cld)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=131464">
</A>
(13.6)</P>
</TD>
</TR>
</TABLE>
<P CLASS="EquationNumbered">
<A NAME="pgfId=68550">
</A>
<SPAN CLASS="BodyComputer">
RISE = 0.10 + 0.07 + (1.75 </SPAN>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="BodyComputer">
Cld) FALL = 0.09 + 0.07 + (1.95 </SPAN>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="BodyComputer">
Cld)</SPAN>
(13.5)</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=85448">
</A>
The first two terms in each of these equations represents the intrinsic delay, with the last term in each equation representing the extrinsic delay. We see that the <SPAN CLASS="BodyComputer">
Cld</SPAN>
corresponds to <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
out</SUB>
, <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pu</SUB>
= 1.75 k<SPAN CLASS="Symbol">
W</SPAN>
, and <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
= 1.95 k<SPAN CLASS="Symbol">
W (</SPAN>
<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pu</SUB>
is the pull-up resistance and <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
is the pull-down resistance)<SPAN CLASS="Symbol">
.</SPAN>
</P>
<P CLASS="Body">
<A NAME="pgfId=69203">
</A>
From the data book the pin capacitances for this logic cell are as follows: </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=131553">
</A>
<SPAN CLASS="BodyComputer">
pin I (input) = 0.060 pF pin ZN (output) = 0.038 pF</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=131555">
</A>
(13.7)</P>
</TD>
</TR>
</TABLE>
<P CLASS="EquationNumbered">
<A NAME="pgfId=68608">
</A>
<SPAN CLASS="BodyComputer">
pin I (input) = 0.060 pF pin ZN (output) = 0.038 pF</SPAN>
(13.6)</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=58757">
</A>
Thus, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
= 0.038 pF and we can calculate the component of the intrinsic delay due to the output pin capacitance as follows: </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnLeft">
<A NAME="pgfId=131576">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pu</SUB>
= 0.038 <SPAN CLASS="Symbol">
¥</SPAN>
1.75 = 0.0665 ns and <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
= 0.038 <SPAN CLASS="Symbol">
¥</SPAN>
1.95 = 0.0741 ns</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=131578">
</A>
(13.8)</P>
</TD>
</TR>
</TABLE>
<P CLASS="EquationNumbered">
<A NAME="pgfId=69051">
</A>
<SPAN CLASS="EquationVariables">
C</SPAN>
<A NAME="11900">
</A>
<SUB CLASS="SubscriptVariable">
p</SUB>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pu</SUB>
= 0.038 <SPAN CLASS="Symbol">
¥</SPAN>
1.75 = 0.0665 ns and <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
= 0.038 <SPAN CLASS="Symbol">
¥</SPAN>
1.95 = 0.0741 ns(13.7)</P>
<P CLASS="Body">
<A NAME="pgfId=85429">
</A>
Suppose <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
qr</SUB>
and <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
qf</SUB>
are the parasitic delays for the rising and falling waveforms respectively. By comparing the data book equations for the rise and fall delays with Eq. <A HREF="CH13.6.htm#38868" CLASS="XRef">
</A>
and <A HREF="CH13.6.htm#11900" CLASS="XRef">
13.7</A>
, we can identify <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
qr</SUB>
= 0.10 ns and <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
qf</SUB>
= 0.09 ns. </P>
<P CLASS="Body">
<A NAME="pgfId=85436">
</A>
Now we can explain the timing section of the <SPAN CLASS="BodyComputer">
in01d0</SPAN>
model (<A HREF="CH13.5.htm#20815" CLASS="XRef">
Section 13.5.3</A>
),</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=85437">
</A>
<B CLASS="Keyword">
specify</B>
<B CLASS="Keyword">
specparam</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=58721">
</A>
InCap$i = 0.060, OutCap$zn = 0.038, MaxLoad$zn = 1.538,</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=58722">
</A>
R_Ramp$i$zn = 0.542:0.980:1.750, F_Ramp$i$zn = 0.605:1.092:1.950;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=58723">
</A>
<B CLASS="Keyword">
specparam</B>
cell_count = 1.000000; <B CLASS="Keyword">
specparam</B>
Transistors = 4 ;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=58724">
</A>
<B CLASS="Keyword">
specparam</B>
Power = 1.400000; <B CLASS="Keyword">
specparam</B>
MaxLoadedRamp = 3 ;</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=69271">
</A>
(i=>zn)=(0.031:0.056:0.100, 0.028:0.050:0.090); </P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=69272">
</A>
The parameter <SPAN CLASS="BodyComputer">
OutCap$zn</SPAN>
is <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
. The maximum value of the parameter <SPAN CLASS="BodyComputer">
R_Ramp$i$zn</SPAN>
is <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pu</SUB>
, and the maximum value of parameter <SPAN CLASS="BodyComputer">
F_Ramp$i$zn</SPAN>
is <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
. Finally, the maximum values of the fixed-delay triplets correspond to <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
qr</SUB>
and <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
qf</SUB>
.</P>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=3298">
</A>
13.6.1 Using a Library Data Book</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=69329">
</A>
ASIC library data books typically contain two types of information for each cell in the library—capacitance loading and delay. <A HREF="CH13.6.htm#42628" CLASS="XRef">
Table 13.7</A>
shows the input capacitances for the inverter family for both an <A NAME="marker=69330">
</A>
<SPAN CLASS="Definition">
area-optimized library</SPAN>
(small) and a <A NAME="marker=69331">
</A>
<SPAN CLASS="Definition">
performance-optimized library</SPAN>
(fast). </P>
<P CLASS="Body">
<A NAME="pgfId=74585">
</A>
From <A HREF="CH13.6.htm#42628" CLASS="XRef">
Table 13.7</A>
, the input capacitance of the small library version of the <SPAN CLASS="BodyComputer">
inv1</SPAN>
(a 1X inverter gate) is 0.034 pF. Any logic cell that is driving an <SPAN CLASS="BodyComputer">
inv1</SPAN>
from the small library sees this as a load capacitance. This capacitance consists of the gate capacitance of a <SPAN CLASS="Emphasis">
p</SPAN>
-channel transistor, the gate capacitance of an <SPAN CLASS="Emphasis">
n</SPAN>
-channel transistor, and the internal cell routing. Similarly, 0.145 pF is the input capacitance of a fast <SPAN CLASS="BodyComputer">
inv1</SPAN>
. We can deduce that the transistors in the fast library are approximately 0.145 / 0.034 ⊕ 4 times larger than those in the small version. The small library and fast library may not have the same cell height (they usually do not), so that we cannot mix cells from different libraries in the same standard-cell area.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="6">
<P CLASS="TableTitle">
<A NAME="pgfId=1135">
</A>
TABLE 13.7 <A NAME="42628">
</A>
Input capacitances for an inverter family (pF).1</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1147">
</A>
<SPAN CLASS="TableHeads">
Library</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1159">
</A>
<SPAN CLASS="TableHeads">
inv1</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1161">
</A>
<SPAN CLASS="TableHeads">
invh<A HREF="#pgfId=32855" CLASS="footnote">
1</A>
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1163">
</A>
<SPAN CLASS="TableHeads">
invs</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1165">
</A>
<SPAN CLASS="TableHeads">
inv8</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1167">
</A>
<SPAN CLASS="TableHeads">
inv12</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=1193">
</A>
Area</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1195">
</A>
0.034 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1197">
</A>
0.067 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1199">
</A>
0.133 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1201">
</A>
0.265 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1203">
</A>
0.397</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=1217">
</A>
Performance</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1219">
</A>
0.145 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1221">
</A>
0.292 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1223">
</A>
0.584 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1225">
</A>
1.169 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=1227">
</A>
1.753 </P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=119002">
</A>
The delay table for a 2:1 MUX is shown in <A HREF="CH13.6.htm#11038" CLASS="XRef">
Table 13.8</A>
. For example, <SPAN CLASS="BodyComputer">
DO/</SPAN>
to <SPAN CLASS="BodyComputer">
Z/</SPAN>
, indicates the path delay from the <SPAN CLASS="BodyComputer">
DO</SPAN>
input rising to the <SPAN CLASS="BodyComputer">
Z</SPAN>
output rising. Rising delay is denoted by <SPAN CLASS="BodyComputer">
'/'</SPAN>
and falling delay by <SPAN CLASS="BodyComputer">
'\'</SPAN>
.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="6">
<P CLASS="TableTitle">
<A NAME="pgfId=119007">
</A>
TABLE 13.8 <A NAME="11038">
</A>
Delay information for a 2:1 MUX.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=119019">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
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