ch13.7.htm

介绍asci设计的一本书

, is 4.5  ns. The delay, t<SUB CLASS="Subscript">
QO</SUB>
, due to the output buffer cell <SPAN CLASS="BodyComputer">
OUTBUF</SPAN>
, instance name <SPAN CLASS="BodyComputer">
OUTBUF_33</SPAN>
, is 3.7  ns. The longest path between clock-pad input and the output, t<SUB CLASS="Subscript">
CO</SUB>
, is thus  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="EquationAlign">
<A NAME="pgfId=132741">
 </A>
t<SUB CLASS="Subscript">
CO</SUB>
 = t<SUB CLASS="Subscript">
IC</SUB>
 + t<SUB CLASS="Subscript">
CQ</SUB>
 + t<SUB CLASS="Subscript">
QO</SUB>
  =  16.1  ns  .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=132743">
 </A>
(13.23)</P>
</TD>
</TR>
</TABLE>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=71366">
 </A>
This is the critical path and limits the operating frequency to (1  /  16.1  ns)  <SPAN CLASS="Symbol">
&#170;</SPAN>
  62  MHz.</P>
<P CLASS="Body">
<A NAME="pgfId=71385">
 </A>
When we created a start set using <SPAN CLASS="BodyComputer">
CLKBUF_30:PAD</SPAN>
, the timing analyzer told us that this set consisted of two pins. We can list the names of the two pins as follows:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=38753">
 </A>
timer&gt; showset clockpad</P>
<P CLASS="Computer">
<A NAME="pgfId=38754">
 </A>
Pin name                   Net name                   Macro name</P>
<P CLASS="Computer">
<A NAME="pgfId=38755">
 </A>
CLKBUF_30/U0:PAD           &lt;no net&gt;                   CLKEXT_0</P>
<P CLASS="Computer">
<A NAME="pgfId=38756">
 </A>
CLKBUF_30/U1:PAD           DEF_NET_145                CLKTRI_0</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=38757">
 </A>
2 pins</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=78503">
 </A>
The clock-buffer instance name, <SPAN CLASS="BodyComputer">
CLKBUF_30/U0</SPAN>
, is hierarchical (with a <SPAN CLASS="BodyComputer">
'/'</SPAN>
 hierarchy separator). This indicates that there is more than one instance inside the clock-buffer cell, <SPAN CLASS="BodyComputer">
CLKBUF_30</SPAN>
. Instance <SPAN CLASS="BodyComputer">
CLKBUF_30/U0</SPAN>
 is the input driver, instance <SPAN CLASS="BodyComputer">
CLKBUF_30/U1</SPAN>
 is the output driver (which is disabled and unused in this case).</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=38762">
 </A>
13.7.4&nbsp;External Setup Time</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=38939">
 </A>
Each of the six chip data inputs must satisfy the following set-up equation:  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="EquationAlign">
<A NAME="pgfId=132727">
 </A>
t<SUB CLASS="Subscript">
SU</SUB>
  (external) &gt; t<SUB CLASS="Subscript">
SU</SUB>
  (internal)  &#8211;  (clock delay)  +  (data delay</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=132729">
 </A>
<A NAME="27243">
 </A>
(13.24)</P>
</TD>
</TR>
</TABLE>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=38821">
 </A>
(where both clock and data delays end at the same flip-flop instance). We find the clock delays in Eq.&nbsp;<A HREF="CH13.7.htm#27243" CLASS="XRef">
13.24</A>
 using the clock input pin as the start set and the end set <SPAN CLASS="BodyComputer">
'clock'</SPAN>
. The timing analyzer tells us all 16 clock path delays are the same at 7.9  ns in our design, and the clock skew is thus zero. Actel&#8217;s clock distribution system minimizes clock skew, but clock skew will not always be zero. From the discussion in <A HREF="CH13.7.htm#26379" CLASS="XRef">
Section&nbsp;13.7.1</A>
, we see there is no possibility of internal hold-time violations with a clock skew of zero. </P>
<P CLASS="Body">
<A NAME="pgfId=38925">
 </A>
Next, we find the data delays in Eq,&nbsp;<A HREF="CH13.7.htm#27243" CLASS="XRef">
13.24</A>
 using a start set of all input pads and an end set of <SPAN CLASS="BodyComputer">
'gated'</SPAN>
,</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=38857">
 </A>
timer&gt; longest</P>
<P CLASS="Computer">
<A NAME="pgfId=93977">
 </A>
... lines omitted ...</P>
<P CLASS="Computer">
<A NAME="pgfId=93979">
 </A>
&nbsp;1st  longest path to all endpins</P>
<P CLASS="Computer">
<A NAME="pgfId=38874">
 </A>
Rank Total Start pin      First Net     End Net       End pin</P>
<P CLASS="Computer">
<A NAME="pgfId=38875">
 </A>
 10   10.0 INBUF_26:PAD   DEF_NET_1320  DEF_NET_1320  a_r_ff_b0:D</P>
<P CLASS="Computer">
<A NAME="pgfId=38876">
 </A>
 11    9.7 INBUF_28:PAD   DEF_NET_1380  DEF_NET_1380  b_r_ff_b1:D</P>
<P CLASS="Computer">
<A NAME="pgfId=38877">
 </A>
 12    9.4 INBUF_25:PAD   DEF_NET_1290  DEF_NET_1290  a_r_ff_b1:D</P>
<P CLASS="Computer">
<A NAME="pgfId=38878">
 </A>
 13    9.3 INBUF_27:PAD   DEF_NET_1350  DEF_NET_1350  b_r_ff_b2:D</P>
<P CLASS="Computer">
<A NAME="pgfId=38879">
 </A>
 14    9.2 INBUF_29:PAD   DEF_NET_1410  DEF_NET_1410  b_r_ff_b0:D</P>
<P CLASS="Computer">
<A NAME="pgfId=38880">
 </A>
 15    9.1 INBUF_24:PAD   DEF_NET_1260  DEF_NET_1260  a_r_ff_b2:D</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=38881">
 </A>
16 pins</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=38926">
 </A>
We are only interested in the last six paths of this analysis (rank 10&#8211;15) that describe the delays from each data input pad (<SPAN CLASS="BodyComputer">
a[0]</SPAN>
, <SPAN CLASS="BodyComputer">
a[1]</SPAN>
, <SPAN CLASS="BodyComputer">
a[2]</SPAN>
, <SPAN CLASS="BodyComputer">
b[0]</SPAN>
, <SPAN CLASS="BodyComputer">
b[1]</SPAN>
, <SPAN CLASS="BodyComputer">
b[2]</SPAN>
) to the D input of a flip-flop. The maximum data delay, 10  ns, occurs on input buffer instance name <SPAN CLASS="BodyComputer">
INBUF_26</SPAN>
 (pad 26); pin <SPAN CLASS="BodyComputer">
INBUF_26:PAD</SPAN>
 is node <SPAN CLASS="BodyComputer">
a_0_</SPAN>
 in the EDIF file or input <SPAN CLASS="BodyComputer">
a[0]</SPAN>
 in our behavioral model. The six t<SUB CLASS="Subscript">
SU</SUB>
  (external) equations corresponding to Eq,&nbsp;<A HREF="CH13.7.htm#27243" CLASS="XRef">
13.24</A>
 may be reduced to the following worst-case relation:  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=132856">
 </A>
t<SUB CLASS="Subscript">
SU</SUB>
  (external)<SUB CLASS="Subscript">
max</SUB>
 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="EquationAlign">
<A NAME="pgfId=132858">
 </A>
&gt;   t<SUB CLASS="Subscript">
SU</SUB>
  (internal)  &#8211;  7.9  ns  + max  (9.1  ns, 10.0  ns)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=132863">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="EquationAlign">
<A NAME="pgfId=132865">
 </A>
&gt;   t<SUB CLASS="Subscript">
SU</SUB>
  (internal)  +  2.1  ns</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=132867">
 </A>
(13.25)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=75081">
 </A>
We calculated the clock and data delay terms in Eq.&nbsp;<A HREF="CH13.7.htm#27243" CLASS="XRef">
13.24</A>
 separately, but timing analyzers can normally perform a single analysis as follows:  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="EquationAlign">
<A NAME="pgfId=132877">
 </A>
t<SUB CLASS="Subscript">
SU</SUB>
  (external)<SUB CLASS="Subscript">
max</SUB>
 &gt; t<SUB CLASS="Subscript">
SU</SUB>
  (internal)  &#8211;    (clock delay  &#8211;  data delay)<SUB CLASS="Subscript">
min</SUB>
 .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=132879">
 </A>
(13.26)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=75223">
 </A>
Finally, we check that there is no external hold-time requirement. That is to say, we must check that t<SUB CLASS="Subscript">
SU</SUB>
  (external) is never negative or  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=132890">
 </A>
t<SUB CLASS="Subscript">
SU</SUB>
  (external)<SUB CLASS="Subscript">
min</SUB>
 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="EquationAlign">
<A NAME="pgfId=132892">
 </A>
&gt; t<SUB CLASS="Subscript">
SU</SUB>
  (internal)  &#8211;    (clock delay  &#8211;  data delay)<SUB CLASS="Subscript">
max</SUB>
 &gt; 0</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnRight">
<A NAME="pgfId=132896">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="EquationAlign">
<A NAME="pgfId=132898">
 </A>
&gt; t<SUB CLASS="Subscript">
SU</SUB>
  (internal)  +  1.2  ns &gt; 0 .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=132900">
 </A>
(13.27)</P>
</TD>
</TR>
</TABLE>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=75293">
 </A>
Since t<SUB CLASS="Subscript">
SU</SUB>
  (internal)   is always positive on Actel FPGAs, t<SUB CLASS="Subscript">
SU</SUB>
  (external)<SUB CLASS="Subscript">
min</SUB>
 is always positive for this design. In large ASICs, with large clock delays, it is possible to have external hold-time requirements on inputs. This is the reason that some FPGAs (Xilinx, for example) have programmable delay elements that deliberately increase the data delay and eliminate irksome external hold-time requirements.</P>
</DIV>
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