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<H1 CLASS="Heading1">
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13.7 <A NAME="13759">
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Static Timing Analysis</H1>
<DIV>
<IMG SRC="CH13-1.gif">
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<P CLASS="BodyAfterHead">
<A NAME="pgfId=3654">
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We return to the <A NAME="marker=118197">
</A>
comparator/MUX example to see how timing analysis is applied to sequential logic. We shall use the same input code (<SPAN CLASS="BodyComputer">
comp_mux.v</SPAN>
in <A HREF="CH13.2.htm#16644" CLASS="XRef">
Section 13.2</A>
), but this time we shall target the design to an Actel FPGA. </P>
<P CLASS="Body">
<A NAME="pgfId=90847">
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Before routing we obtain the following static timing analysis:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=38225">
</A>
Instance name in pin-->out pin tr total incr cell</P>
<P CLASS="Computer">
<A NAME="pgfId=38226">
</A>
--------------------------------------------------------------------</P>
<P CLASS="Computer">
<A NAME="pgfId=38227">
</A>
END_OF_PATH</P>
<P CLASS="Computer">
<A NAME="pgfId=38228">
</A>
outp_2_ R 27.26</P>
<P CLASS="Computer">
<A NAME="pgfId=38229">
</A>
OUT1 : D--->PAD R 27.26 7.55 OUTBUF</P>
<P CLASS="Computer">
<A NAME="pgfId=38230">
</A>
I_1_CM8 : S11--->Y R 19.71 4.40 CM8</P>
<P CLASS="Computer">
<A NAME="pgfId=38231">
</A>
I_2_CM8 : S11--->Y R 15.31 5.20 CM8</P>
<P CLASS="Computer">
<A NAME="pgfId=38232">
</A>
I_3_CM8 : S11--->Y R 10.11 4.80 CM8</P>
<P CLASS="Computer">
<A NAME="pgfId=38233">
</A>
IN1 : PAD--->Y R 5.32 5.32 INBUF</P>
<P CLASS="Computer">
<A NAME="pgfId=38234">
</A>
a_2_ R 0.00 0.00</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=38223">
</A>
BEGIN_OF_PATH</P>
<P CLASS="Body">
<A NAME="pgfId=96745">
</A>
The estimated prelayout critical path delay is nearly 30 ns including the I/O-cell delays (ACT 3, worst-case, standard speed grade). This limits the operating frequency to 33 MHz (assuming we can get the signals to and from the chip pins with no further delays—highly unlikely). The operating frequency can be increased by pipelining the design as follows (by including three register stages: at the inputs, the outputs, and between the comparison and the select functions):</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=38167">
</A>
// comp_mux_rrr.v</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=38015">
</A>
<B CLASS="Keyword">
module</B>
comp_mux_rrr(a, b, clock, outp); </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=38043">
</A>
<B CLASS="Keyword">
input</B>
[2:0] a, b; output [2:0] outp; <B CLASS="Keyword">
input</B>
clock;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=38126">
</A>
<B CLASS="Keyword">
reg</B>
[2:0] a_r, a_rr, b_r, b_rr, outp; <B CLASS="Keyword">
reg</B>
sel_r;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=38164">
</A>
<B CLASS="Keyword">
wire</B>
sel = ( a_r <= b_r ) ? 0 : 1; </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=38177">
</A>
<B CLASS="Keyword">
always</B>
@ (<B CLASS="Keyword">
posedge</B>
clock) <B CLASS="Keyword">
begin</B>
a_r <= a; b_r <= b; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=38178">
</A>
<B CLASS="Keyword">
always</B>
@ (<B CLASS="Keyword">
posedge</B>
clock) <B CLASS="Keyword">
begin</B>
a_rr <= a_r; b_rr <= b_r; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=38179">
</A>
<B CLASS="Keyword">
always</B>
@ (<B CLASS="Keyword">
posedge</B>
clock) outp <= sel_r ? b_rr : a_rr;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=38020">
</A>
<B CLASS="Keyword">
always</B>
@ (<B CLASS="Keyword">
posedge</B>
clock) sel_r <= sel;</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=38073">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="Body">
<A NAME="pgfId=38941">
</A>
Following synthesis we optimize module <SPAN CLASS="BodyComputer">
comp_mux_rrr</SPAN>
for maximum speed. Static timing analysis gives the following preroute critical paths:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=90903">
</A>
---------------------INPAD to SETUP longest path---------------------</P>
<P CLASS="Computer">
<A NAME="pgfId=38299">
</A>
Rise delay, Worst case</P>
<P CLASS="Computer">
<A NAME="pgfId=38301">
</A>
Instance name in pin-->out pin tr total incr cell</P>
<P CLASS="Computer">
<A NAME="pgfId=38302">
</A>
--------------------------------------------------------------------</P>
<P CLASS="Computer">
<A NAME="pgfId=38303">
</A>
END_OF_PATH</P>
<P CLASS="Computer">
<A NAME="pgfId=38304">
</A>
D.a_r_ff_b2 R 4.52 0.00 DF1</P>
<P CLASS="Computer">
<A NAME="pgfId=38305">
</A>
INBUF_24 : PAD--->Y R 4.52 4.52 INBUF</P>
<P CLASS="Computer">
<A NAME="pgfId=38306">
</A>
a_2_ R 0.00 0.00</P>
<P CLASS="Computer">
<A NAME="pgfId=38307">
</A>
BEGIN_OF_PATH</P>
<P CLASS="Computer">
<A NAME="pgfId=38308">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=38310">
</A>
---------------------CLOCK to SETUP longest path---------------------</P>
<P CLASS="Computer">
<A NAME="pgfId=38311">
</A>
Rise delay, Worst case</P>
<P CLASS="Computer">
<A NAME="pgfId=38312">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=38313">
</A>
Instance name in pin-->out pin tr total incr cell</P>
<P CLASS="Computer">
<A NAME="pgfId=38314">
</A>
--------------------------------------------------------------------</P>
<P CLASS="Computer">
<A NAME="pgfId=38315">
</A>
END_OF_PATH</P>
<P CLASS="Computer">
<A NAME="pgfId=38316">
</A>
D.sel_r_ff R 9.99 0.00 DF1</P>
<P CLASS="Computer">
<A NAME="pgfId=38317">
</A>
I_1_CM8 : S10--->Y R 9.99 0.00 CM8</P>
<P CLASS="Computer">
<A NAME="pgfId=38318">
</A>
I_3_CM8 : S00--->Y R 9.99 4.40 CM8</P>
<P CLASS="Computer">
<A NAME="pgfId=38319">
</A>
a_r_ff_b1 : CLK--->Q R 5.60 5.60 DF1</P>
<P CLASS="Computer">
<A NAME="pgfId=38320">
</A>
BEGIN_OF_PATH</P>
<P CLASS="Computer">
<A NAME="pgfId=90861">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=90862">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=90863">
</A>
---------------------CLOCK to OUTPAD longest path--------------------</P>
<P CLASS="Computer">
<A NAME="pgfId=38324">
</A>
Rise delay, Worst case</P>
<P CLASS="Computer">
<A NAME="pgfId=38325">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=38326">
</A>
Instance name in pin-->out pin tr total incr cell</P>
<P CLASS="Computer">
<A NAME="pgfId=38327">
</A>
--------------------------------------------------------------------</P>
<P CLASS="Computer">
<A NAME="pgfId=38328">
</A>
END_OF_PATH</P>
<P CLASS="Computer">
<A NAME="pgfId=38329">
</A>
outp_2_ R 11.95</P>
<P CLASS="Computer">
<A NAME="pgfId=38330">
</A>
OUTBUF_31 : D--->PAD R 11.95 7.55 OUTBUF</P>
<P CLASS="Computer">
<A NAME="pgfId=38331">
</A>
outp_ff_b2 : CLK--->Q R 4.40 4.40 DF1</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=38284">
</A>
BEGIN_OF_PATH</P>
<P CLASS="Body">
<A NAME="pgfId=70473">
</A>
The timing analyzer has examined the following:</P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=70474">
</A>
Paths that start at an input pad and end on the data input of a sequential logic cell (the D input to a D flip-flop, for example). We might call this an <SPAN CLASS="Definition">
entry path</SPAN>
<A NAME="marker=118205">
</A>
(or <A NAME="marker=118295">
</A>
input-to-D path) to a pipelined design. The longest <SPAN CLASS="Definition">
entry delay</SPAN>
<A NAME="marker=118253">
</A>
(or <A NAME="marker=118294">
</A>
input-to-setup delay) is 4.52 ns.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=70475">
</A>
Paths that start at a clock input to a sequential logic cell and end at the data input of a sequential logic cell. This is a <SPAN CLASS="Definition">
stage path</SPAN>
<A NAME="marker=118206">
</A>
(<A NAME="marker=118217">
</A>
register-to-register path or <A NAME="marker=118218">
</A>
clock-to-D path) in a pipeline stage. The longest <SPAN CLASS="Definition">
stage delay</SPAN>
<A NAME="marker=118254">
</A>
(<A NAME="marker=118297">
</A>
clock-to-D delay) is 9.99 ns.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=70478">
</A>
Paths that start at a sequential logic cell output and end at an output pad. This is an <SPAN CLASS="Definition">
exit path</SPAN>
<A NAME="marker=118207">
</A>
(<A NAME="marker=118229">
</A>
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