📄 ch13.3.htm
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<A NAME="pgfId=97607">
</A>
2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97609">
</A>
size of trireg net capacitor</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97612">
</A>
<A NAME="marker=97611">
</A>
medium</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97615">
</A>
<SPAN CLASS="BodyComputer">
Me</SPAN>
<A NAME="marker=97614">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97617">
</A>
small capacitor</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97619">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97621">
</A>
size of trireg net capacitor</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97624">
</A>
<A NAME="marker=97623">
</A>
small</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97627">
</A>
<SPAN CLASS="BodyComputer">
Sm</SPAN>
<A NAME="marker=97626">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97629">
</A>
high impedance</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97631">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97633">
</A>
not applicable</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97636">
</A>
<A NAME="marker=97635">
</A>
highz</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97639">
</A>
<SPAN CLASS="BodyComputer">
Hi</SPAN>
<A NAME="marker=97638">
</A>
</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=35087">
</A>
The <A NAME="marker=117589">
</A>
IEEE Std 1164-1993 logic system defines a variable type, <SPAN CLASS="BodyComputer">
std_ulogic</SPAN>
, with the nine logic values shown in <A HREF="CH13.3.htm#16736" CLASS="XRef">
Table 13.6</A>
. When we wish to simulate logic cells using this logic system, we must define the primitive-gate operations. We also need to define the process of <A NAME="marker=35093">
</A>
<SPAN CLASS="Definition">
VHDL signal resolution</SPAN>
using <A NAME="marker=35094">
</A>
<SPAN CLASS="Definition">
VHDL signal-resolution functions</SPAN>
. For example, the function in the IEEE Std_Logic_1164 package that defines the <SPAN CLASS="BodyComputer">
and</SPAN>
operation is as follows<A HREF="#pgfId=120096" CLASS="footnote">
1</A>
:</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=97668">
</A>
TABLE 13.6 <A NAME="16736">
</A>
The nine-value logic system, IEEE Std 1164-1993.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97679">
</A>
<SPAN CLASS="TableHeads">
Logic state</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97681">
</A>
<SPAN CLASS="TableHeads">
Logic value</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97683">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97685">
</A>
<SPAN CLASS="TableHeads">
Logic state</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97687">
</A>
<SPAN CLASS="TableHeads">
Logic value</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97689">
</A>
<SPAN CLASS="BodyComputer">
'0'</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97691">
</A>
strong low</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97693">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97695">
</A>
<SPAN CLASS="BodyComputer">
'X'</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97697">
</A>
strong unknown</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97699">
</A>
<SPAN CLASS="BodyComputer">
'1'</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97701">
</A>
strong high</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97703">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97705">
</A>
<SPAN CLASS="BodyComputer">
'W'</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97707">
</A>
weak unknown</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97709">
</A>
<SPAN CLASS="BodyComputer">
'L'</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97711">
</A>
weak low</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97713">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97715">
</A>
<SPAN CLASS="BodyComputer">
'Z'</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97717">
</A>
high impedance</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97719">
</A>
<SPAN CLASS="BodyComputer">
'H'</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97721">
</A>
weak high</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97723">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97725">
</A>
<SPAN CLASS="BodyComputer">
'-'</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97727">
</A>
don’t care</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97729">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97731">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97733">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97735">
</A>
<SPAN CLASS="BodyComputer">
'U'</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97737">
</A>
uninitialized</P>
</TD>
</TR>
</TABLE>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=2740">
</A>
function "and"(l,r : std_ulogic_vector) return std_ulogic_vector is</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=2742">
</A>
alias lv : std_ulogic_vector (1 to l'LENGTH ) is l;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=2744">
</A>
alias rv : std_ulogic_vector (1 to r'LENGTH ) is r;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=2746">
</A>
variable result : std_ulogic_vector (1 to l'LENGTH );</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30939">
</A>
constant and_table : stdlogic_table := ( </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30940">
</A>
-----------------------------------------------------------</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30941">
</A>
--| U X 0 1 Z W L H - | |</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30942">
</A>
-----------------------------------------------------------</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30943">
</A>
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30944">
</A>
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30945">
</A>
( '0', '0', '0', '0', '0', '0', '0', 'U', '0' ), -- | 0 |</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30946">
</A>
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30947">
</A>
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30948">
</A>
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30949">
</A>
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30950">
</A>
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=30951">
</A>
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | - |);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=2748">
</A>
begin </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=2750">
</A>
if (l'LENGTH /= r'LENGTH) then assert false report </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=26902">
</A>
"arguments of overloaded 'and' operator are not of the same</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=97511">
</A>
length"</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=26903">
</A>
severity failure;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=2758">
</A>
else</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=2760">
</A>
for i in result'RANGE loop</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=2762">
</A>
result(i) := and_table ( lv(i), rv(i) );</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=2764">
</A>
end loop;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=2766">
</A>
end if;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=2768">
</A>
return result;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=2770">
</A>
end "and";</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=30931">
</A>
If <SPAN CLASS="BodyComputer">
a = 'X'</SPAN>
and <SPAN CLASS="BodyComputer">
b = '0'</SPAN>
, then <SPAN CLASS="BodyComputer">
(a and b)</SPAN>
is <SPAN CLASS="BodyComputer">
'0'</SPAN>
no matter whether <SPAN CLASS="BodyComputer">
a</SPAN>
is, in fact, <SPAN CLASS="BodyComputer">
'0'</SPAN>
or <SPAN CLASS="BodyComputer">
'1'</SPAN>
. </P>
</DIV>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="Footnote">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=120096">
</A>
IEEE Std 1164-1993, © Copyright 1993 IEEE. All rights reserved.</P>
</DIV>
</DIV>
<HR><P>[ <A HREF="CH13.htm">Chapter start</A> ] [ <A HREF="CH13.2.htm">Previous page</A> ] [ <A HREF="CH13.4.htm">Next page</A> ]</P></BODY>
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