ch13.3.htm

介绍asci设计的一本书

13.3.2&nbsp;<A NAME="32272">
 </A>
Logic Strength</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=117354">
 </A>
In CMOS logic we use <SPAN CLASS="Emphasis">
n</SPAN>
-channel transistors to produce a logic level 'zero' (with a forcing strength) and we use <SPAN CLASS="Emphasis">
p</SPAN>
-channel transistors to force a logic level 'one'. An <SPAN CLASS="Emphasis">
n</SPAN>
-channel transistor provides a weak logic level 'one'. This is a new logic value, a <A NAME="marker=117355">
 </A>
<SPAN CLASS="Definition">
resistive 'one'</SPAN>
, which has a logic level of 'one', but with <A NAME="marker=117356">
 </A>
<SPAN CLASS="Definition">
resistive strength</SPAN>
. Similarly, a <SPAN CLASS="Emphasis">
p</SPAN>
-channel transistor produces a <A NAME="marker=117357">
 </A>
<SPAN CLASS="Definition">
resistive 'zero'</SPAN>
. A resistive strength is not as strong as a forcing strength. At a high-impedance node there is nothing to keep the node at any logic level. We say that the logic strength is <SPAN CLASS="Definition">
high impedance</SPAN>
<A NAME="marker=117358">
 </A>
. A high-impedance strength is the weakest strength and we can treat it as either a very high-resistance connection to a power supply or no connection at all.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=117363">
 </A>
TABLE&nbsp;13.4&nbsp;<A NAME="11891">
 </A>
A 12-state logic system.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=117373">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=117375">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="3">
<P CLASS="TableFirst">
<A NAME="pgfId=117377">
 </A>
Logic level</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableLeft">
<A NAME="pgfId=117383">
 </A>
	<SPAN CLASS="TableHeads">
Logic strength</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=117387">
 </A>
<SPAN CLASS="TableHeads">
zero</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=117389">
 </A>
<SPAN CLASS="TableHeads">
unknown</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=117391">
 </A>
<SPAN CLASS="TableHeads">
one</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="4" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=117393">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117395">
 </A>
<SPAN CLASS="TableHeads">
strong</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117397">
 </A>
S0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117399">
 </A>
SX</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117401">
 </A>
S1</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117405">
 </A>
<SPAN CLASS="TableHeads">
weak</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117407">
 </A>
W0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117409">
 </A>
WX</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117411">
 </A>
W1</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117415">
 </A>
<SPAN CLASS="TableHeads">
high impedance</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117417">
 </A>
Z0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117419">
 </A>
ZX</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117421">
 </A>
Z1</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117425">
 </A>
<SPAN CLASS="TableHeads">
unknown</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117427">
 </A>
U0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117429">
 </A>
UX</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117431">
 </A>
U1</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=117432">
 </A>
With the introduction of logic strength, a logic value may now have two properties: level and strength. Suppose we were to measure a voltage at a node <SPAN CLASS="BodyComputer">
N</SPAN>
 with a digital voltmeter (with a very high input impedance). Suppose the measured voltage at node <SPAN CLASS="BodyComputer">
N</SPAN>
 was 4.98  V (and the measured positive supply, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
  =  5.00  V). We can say that node <SPAN CLASS="BodyComputer">
N</SPAN>
 is a logic level 'one', but we do not know the logic strength. Now suppose you connect one end of a 1  k<SPAN CLASS="Symbol">
W</SPAN>
 resistor to node <SPAN CLASS="BodyComputer">
N</SPAN>
, the other to GND, and the voltage at <SPAN CLASS="BodyComputer">
N</SPAN>
 changes to 4.95  V. Now we can say that whatever is driving node <SPAN CLASS="BodyComputer">
N</SPAN>
 has a strong forcing strength. In fact, we know that whatever is driving <SPAN CLASS="BodyComputer">
N</SPAN>
 is capable of supplying a current of at least 4.95  V  /  1  k<SPAN CLASS="Symbol">
W</SPAN>
  &#8853;  5  mA. Depending on the logic-value system we are using, we can assign a logic value to <SPAN CLASS="BodyComputer">
N</SPAN>
. If we allow all possible combinations of logic level with logic strength, we end up with a matrix of logic values and logic states. <A HREF="CH13.3.htm#11891" CLASS="XRef">
Table&nbsp;13.4</A>
 shows the 12 states that result with three logic levels (zero, one, unknown) and four logic strengths (strong, weak, high-impedance, and unknown). In this logic system, node <SPAN CLASS="BodyComputer">
N</SPAN>
 has logic value <SPAN CLASS="BodyComputer">
S1</SPAN>
&#8212;a logic level of 'one' with a logic strength of 'strong'.</P>
<P CLASS="Body">
<A NAME="pgfId=97517">
 </A>
The <SPAN CLASS="Definition">
Verilog logic system</SPAN>
<A NAME="marker=97516">
 </A>
 has three logic levels that are called <SPAN CLASS="BodyComputer">
'1'</SPAN>
, <SPAN CLASS="BodyComputer">
'0'</SPAN>
, and <SPAN CLASS="BodyComputer">
'x'</SPAN>
; and the eight logic strengths shown in <A HREF="CH13.3.htm#36966" CLASS="XRef">
Table&nbsp;13.5</A>
. The designer does not normally see the logic values that result&#8212;only the three logic levels.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=97523">
 </A>
TABLE&nbsp;13.5&nbsp;<A NAME="36966">
 </A>
Verilog logic strengths.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97535">
 </A>
<SPAN CLASS="TableHeads">
Logic strength</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97537">
 </A>
<SPAN CLASS="TableHeads">
Strength number</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97539">
 </A>
<SPAN CLASS="TableHeads">
	Models</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="Table">
<A NAME="pgfId=97541">
 </A>
<SPAN CLASS="TableHeads">
Abbreviation</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97545">
 </A>
supply drive</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97547">
 </A>
7</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97549">
 </A>
power supply</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97552">
 </A>
<A NAME="marker=97551">
 </A>
supply</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97555">
 </A>
<SPAN CLASS="BodyComputer">
Su</SPAN>
<A NAME="marker=97554">
 </A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97557">
 </A>
strong drive</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97559">
 </A>
6</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97561">
 </A>
default gate and assign output strength</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97564">
 </A>
<A NAME="marker=97563">
 </A>
strong</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97567">
 </A>
<SPAN CLASS="BodyComputer">
St</SPAN>
<A NAME="marker=97566">
 </A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97569">
 </A>
pull drive</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97571">
 </A>
5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97573">
 </A>
gate and assign output strength</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97576">
 </A>
<A NAME="marker=97575">
 </A>
pull</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97579">
 </A>
<SPAN CLASS="BodyComputer">
Pu</SPAN>
<A NAME="marker=97578">
 </A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97581">
 </A>
large capacitor</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97583">
 </A>
4</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97585">
 </A>
size of trireg net capacitor</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97588">
 </A>
<A NAME="marker=97587">
 </A>
large</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97591">
 </A>
<SPAN CLASS="BodyComputer">
La</SPAN>
<A NAME="marker=97590">
 </A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97593">
 </A>
weak drive</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97595">
 </A>
3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97597">
 </A>
gate and assign output strength</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97600">
 </A>
<A NAME="marker=97599">
 </A>
weak</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97603">
 </A>
<SPAN CLASS="BodyComputer">
We</SPAN>
<A NAME="marker=97602">
 </A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97605">
 </A>
medium capacitor</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">