ch13.c.htm

介绍asci设计的一本书

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		if (count = 0) then carry &lt;= 1; else carry &lt;= 0; end if;</P>
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		end case;</P>
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	end if;</P>
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end process;</P>
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end behave;</P>
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13.27&nbsp;(***VITAL flip-flop)&nbsp;The following VITAL code models a D flip-flop:</P>
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LIBRARY ieee; USE ieee.Std_Logic_1164.all; </P>
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USE ieee.Vital_Timing.all; USE ieee.Vital_Primitives.all;</P>
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ENTITY dff IS </P>
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	GENERIC (</P>
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	TimingChecksOn : BOOLEAN := TRUE;</P>
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	XGenerationOn : BOOLEAN := TRUE;</P>
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	InstancePath : STRING := &quot;*&quot;;</P>
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	tipd_Clock :  DelayType01 := (0 ns, 0 ns);</P>
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	tipd_Data :  DelayType01 := (0 ns, 0 ns);</P>
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	tsetup_Data_Clock : DelayType01 := (0 ns, 0 ns);</P>
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	thold_Data_Clock : DelayType01 := (0 ns, 0 ns);</P>
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	tpd_Clock_Q : DelayType01 := (0 ns, 0 ns);</P>
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	tpd_Clock_Qbar : DelayType01 := (0 ns, 0 ns));</P>
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	PORT (Clock, Data: Std_Logic; Q,Qbar:OUT Std_Logic);</P>
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END dff;</P>
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ARCHITECTURE Gate OF dff IS</P>
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	ATTRIBUTE Vital_Level1 of gate : ARCHITECTURE IS TRUE;</P>
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	SIGNAL Clock_ipd : Std_Logic := 'X';</P>
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	SIGNAL Data_ipd  : Std_Logic := 'X';</P>
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BEGIN</P>
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Wire_Delay:BLOCK BEGIN --  INPUT PATH DELAYs</P>
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	VitalPropagateWireDelay</P>
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		(Clock_ipd, Clock, VitalExtendToFillDelay(tipd_Clock));</P>
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	VitalPropagateWireDelay </P>
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		(Data_ipd, Data, VitalExtendToFillDelay(tipd_Data));</P>
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END BLOCK;</P>
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VitalBehavior : PROCESS (Clock_ipd, Data_ipd)</P>
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	CONSTANT Dff_tab:VitalStateTableType:= (</P>
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--Vio   CLOCK DATA  IQ     Q    QBAR</P>
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( 'X',  '-',  '-',  '-',  'X',  'X' ), -- Timing Violation</P>
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( '-',  '\',  '0',  '-',  '0',  '1' ), -- Active Clock Edge</P>
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( '-',  '\',  '1',  '-',  '1',  '0' ),</P>
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( '-',  '\',  'X',  '-',  'X',  'X' ),</P>
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( '-',  '-',  '0',  '0',  '0',  '1' ), -- X Reduction</P>
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( '-',  '-',  '1',  '1',  '1',  '0' ),</P>
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( '-',  'D',  '-',  '-',  'X',  'X' ), -- X Generation</P>
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( '-',  'B',  '-',  '-',  'S',  'S' ), -- Non-Active Clock Edge</P>
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( '-',  'X',  '-',  '-',  'S',  'S' ));</P>
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-- Anything else generates X on Q and QBAR</P>
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-- Timing Check Results</P>
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	VARIABLE Tviol_Data_Clock : X01 := '0';</P>
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	VARIABLE Tmkr_Data_Clock  : TimeMarkerType;</P>
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-- Functionality Results</P>
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	VARIABLE Violation:X01:='0';</P>
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	VARIABLE PrevData:Std_Logic_Vector(1 to 3):=(OTHERS=&gt;'X');</P>
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	VARIABLE Results:Std_Logic_Vector(1 to 2):=(OTHERS =&gt;'X');</P>
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	ALIAS Q_zd:Std_Logic IS Results(1);</P>
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	ALIAS Qbar_zd:Std_Logic IS Results(2);</P>
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-- Output Glitch Detection Variables</P>
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	VARIABLE Q_GlitchData : GlitchDataType;</P>
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	VARIABLE Qbar_GlitchData : GlitchDataType;</P>
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BEGIN --  Timing Check Section</P>
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	IF (TimingChecksOn) THEN</P>
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	VitalTimingCheck (</P>
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	Data_ipd, &quot;Data&quot;, Clock_ipd, &quot;Clock&quot;,</P>
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	t_setup_hi =&gt; tsetup_Data_Clock(tr01),</P>
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	t_setup_lo =&gt; tsetup_Data_Clock(tr10),</P>
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	t_hold_hi =&gt; thold_Data_Clock(tr01),</P>
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	t_hold_lo =&gt; thold_Data_Clock(tr10),</P>
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	CheckEnabled  =&gt; TRUE,</P>
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	RefTransition =&gt; (Clock_ipd = '0'),</P>
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	HeaderMsg =&gt; InstancePath &amp; &quot;/DFF&quot;,</P>
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	TimeMarker =&gt; Tmkr_Data_Clock, </P>
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	Violation =&gt; Tviol_Data_Clock);</P>
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	END IF;</P>
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--  Functionality Section</P>
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	Violation := Tviol_Data_Clock ;</P>
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	VitalStateTable(StateTable =&gt; Dff_tab,</P>
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	DataIn =&gt; (Violation, Clock_ipd, Data_ipd),</P>
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	NumStates  =&gt; 1,</P>
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	Result =&gt; Results,</P>
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	PreviousDataIn =&gt; PrevData);</P>
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--  Path Delay Section</P>
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	VitalPropagatePathDelay (Q, &quot;Q&quot;, Q_zd,</P>
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	Paths =&gt; (0 =&gt; (Clock_ipd'LAST_EVENT, </P>
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	VitalExtendToFillDelay(tpd_Clock_Q), TRUE),</P>
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		1 =&gt; (Clock_ipd'LAST_EVENT, </P>
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	VitalExtendToFillDelay(tpd_Clock_Q), TRUE)),</P>
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		GlitchData =&gt; Q_GlitchData, </P>
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		GlitchMode =&gt; MessagePlusX, </P>
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		GlitchKind =&gt; OnEvent );</P>
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	VitalPropagatePathDelay ( Qbar, &quot;Qbar&quot;, Qbar_zd,</P>
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		Paths =&gt; (0 =&gt; (Clock_ipd'LAST_EVENT, </P>
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	VitalExtendToFillDelay(tpd_Clock_Qbar), TRUE), </P>
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		1 =&gt; (Clock_ipd'LAST_EVENT, </P>
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	VitalExtendToFillDelay(tpd_Clock_Qbar), TRUE)), </P>
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		GlitchData =&gt; Qbar_GlitchData, </P>
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		GlitchMode =&gt; MessagePlusX, </P>
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		GlitchKind =&gt; OnEvent );</P>
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	END PROCESS;</P>
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END Gate;</P>
<UL>
<LI CLASS="ExercisePartFirst">
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a.&nbsp;(120  min.)&nbsp;Build a testbench for this model.</LI>
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b.&nbsp;(30  min.)&nbsp;Simulate and check the model using your testbench. </LI>
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c.&nbsp;(60  min.)&nbsp;Explain the function of each line.</LI>
<LI CLASS="ExercisePart">
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d.&nbsp;(60  min.)&nbsp;Explain the glitch detection. </LI>
<LI CLASS="ExercisePart">
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e.&nbsp;(120  min.) Explain the unknown propagation behavior.</LI>
</UL>
<P CLASS="ExerciseHead">
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13.28&nbsp;(VCD, 30  min.)&nbsp;Verilog can create a <SPAN CLASS="Definition">
value change dump </SPAN>
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(<SPAN CLASS="Definition">
VCD</SPAN>
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) file:</P>
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<B CLASS="Keyword">
module</B>
 waves; <B CLASS="Keyword">
reg</B>
 clock; <B CLASS="Keyword">
integer</B>
 count;</P>
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<B CLASS="Keyword">
initial</B>
 <B CLASS="Keyword">
begin </B>
clock = 0; count = 0; $dumpvars; #340 $finish; <B CLASS="Keyword">
end</B>
</P>
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<B CLASS="Keyword">
always</B>
 #10 clock = ~ clock;</P>
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<B CLASS="Keyword">
always begin </B>
@ (<B CLASS="Keyword">
negedge</B>
 clock); <B CLASS="Keyword">
if</B>
 (count == 7) count = 0;</P>
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		<B CLASS="Keyword">
else </B>
count = count + 1; <B CLASS="Keyword">
end</B>
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endmodule</B>
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A VCD file contains header information, variable definitions, and the value changes for variables [Verilog LRM 15]. Try and explain the format of the file that results.</P>
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13.29&nbsp;<A NAME="20482">
 </A>
(*Formal verification, 60  min.)&nbsp;(Based on an example by Browne, Clarke, Dill, and Mishra.)&nbsp;A designer needs to fold an 8-bit ripple-carry adder into a small space on an ASIC and check the circuit extracted from the layout. With two 8-bit inputs, <SPAN CLASS="BodyComputer">
A</SPAN>
 and <SPAN CLASS="BodyComputer">
B</SPAN>
, and a 1-bit carry <SPAN CLASS="BodyComputer">
Cin</SPAN>
, exhaustively testing all possible inputs requires 2<SUP CLASS="Superscript">
17</SUP>