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# to check agreement within time tolerance delta (by default 0.1)</P>
<P CLASS="Computer">
<A NAME="pgfId=100325">
</A>
#</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=100326">
</A>
# Use: check file1 file2 [delta]</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=81562">
</A>
13.19 (VITAL, 60 min.) Simulate the model, <SPAN CLASS="BodyComputer">
sdf_testbench</SPAN>
, shown in <A HREF="CH13.5.htm#15313" CLASS="XRef">
Section 13.5.5</A>
, with and without back-annotation timing information in <SPAN CLASS="BodyComputer">
SDF_b.sdf</SPAN>
.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=18133">
</A>
13.20 <A NAME="30225">
</A>
(Formal verification, 60 min.) Write a cheat sheet explaining how to run your formal verification tool. Repeat the example in <A HREF="CH13.8.htm#19438" CLASS="XRef">
Section 13.8.1</A>
.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=97793">
</A>
13.21 (***Beetle problem) (Based on a problem by Seitz.) A planet has many geological gem mazes: A maze covers a square km or so, on a 10 mm grid; a maze cell is 10 mm by 10 mm and gems lie at cell centers; there is a path from every maze cell to every other; on average one in 64 cells has an overhead opening; on average one in seven cells has a single gem; there are no gems under overhead openings.</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=9582">
</A>
You are to design a gem-mining beetle ASIC with the following inputs: a nominal 1 MHz single-phase clock, <SPAN CLASS="BodyComputer">
CLK</SPAN>
; wall sensors: <SPAN CLASS="BodyComputer">
WL</SPAN>
, <SPAN CLASS="BodyComputer">
WR</SPAN>
, <SPAN CLASS="BodyComputer">
WF</SPAN>
, <SPAN CLASS="BodyComputer">
WB</SPAN>
(wall to left/right/forward/behind); light sensors: <SPAN CLASS="BodyComputer">
LL</SPAN>
, <SPAN CLASS="BodyComputer">
LR</SPAN>
, <SPAN CLASS="BodyComputer">
LF</SPAN>
, <SPAN CLASS="BodyComputer">
LB</SPAN>
<SPAN CLASS="BodyComputer">
(</SPAN>
light left/right/forward/behind); low-battery indicator: <SPAN CLASS="BodyComputer">
BLOW</SPAN>
; gem sensor: <SPAN CLASS="BodyComputer">
GEM </SPAN>
(directly over a gem); opening sensor: <SPAN CLASS="BodyComputer">
OPEN </SPAN>
(when under an opening).</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=9589">
</A>
All signals are active high and the light sensor outputs are mutually exclusive. The beetle ASIC must produce the following (mutually exclusive) signals: move forward,<SPAN CLASS="BodyComputer">
MF</SPAN>
; move backward,<SPAN CLASS="BodyComputer">
MB</SPAN>
; turn 90 degrees clockwise,<SPAN CLASS="BodyComputer">
TC</SPAN>
; turn 90 degrees anticlockwise,<SPAN CLASS="BodyComputer">
TA</SPAN>
; pick up a gem,<SPAN CLASS="BodyComputer">
PICKUP</SPAN>
; throw gem up and out of overhead opening,<SPAN CLASS="BodyComputer">
THROWUP</SPAN>
; jump up to surface and shut down,<SPAN CLASS="BodyComputer">
SHUTUP</SPAN>
.</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=9599">
</A>
The beetle specifications and limitations are as follows: Beetles are dropped into the maze to find the gems; beetles must find gems and carry them to an opening; beetles can eject gems through openings; beetles can carry only one gem at a time.</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=9604">
</A>
A beetle move is one of the following: taking one step (moving to an adjacent cell), turning 90 degrees, picking up a gem, ejecting a gem, jumping out of opening—all take the same time and energy. A battery can provide energy for about 200 moves before the low-battery signal comes on. After the low-battery warning is signaled the battery has energy for 50 moves to find an overhead opening, and the beetle must then eject itself for recharging. The cost of the beetle determines that we would like the probability of losing a beetle be below 0.01.</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=9609">
</A>
The following describes a state machine to drive a beetle. Jim Rowson used a state-machine language that he developed—along with the first CAD tool that could automatically create state machines:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=9611">
</A>
# Jim Rowson's beetle</P>
<P CLASS="Computer">
<A NAME="pgfId=9612">
</A>
sm smbtl;</P>
<P CLASS="Computer">
<A NAME="pgfId=9613">
</A>
clock clk;</P>
<P CLASS="Computer">
<A NAME="pgfId=9614">
</A>
reset res --> resetState;</P>
<P CLASS="Computer">
<A NAME="pgfId=9615">
</A>
inputs WL WL WR WB GEM LF LL LR LB OPEN BLOW;</P>
<P CLASS="Computer">
<A NAME="pgfId=9616">
</A>
outputs MF=0 MB=0 TC=0 TA=0 PICKUP=0 THROWUP=0 SHUTUP=0; </P>
<P CLASS="Computer">
<A NAME="pgfId=27021">
</A>
outputs haveAgem SHUTUP;</P>
<P CLASS="Computer">
<A NAME="pgfId=9618">
</A>
let getout = (BLOW|haveAgem) & (LL|LF|LR|LB);</P>
<P CLASS="Computer">
<A NAME="pgfId=26942">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=9619">
</A>
state resetState --> searchState haveAgem=0 SHUTUP=0;</P>
<P CLASS="Computer">
<A NAME="pgfId=9621">
</A>
state searchState</P>
<P CLASS="Computer">
<A NAME="pgfId=9622">
</A>
BLOW & OPEN --> jumpState,</P>
<P CLASS="Computer">
<A NAME="pgfId=9623">
</A>
haveAgem & OPEN --> ejectstate,</P>
<P CLASS="Computer">
<A NAME="pgfId=9624">
</A>
getout & LL --> turnLstate,</P>
<P CLASS="Computer">
<A NAME="pgfId=9625">
</A>
getout & LF --> goFwdState,</P>
<P CLASS="Computer">
<A NAME="pgfId=9626">
</A>
getout & LR --> turnRstate,</P>
<P CLASS="Computer">
<A NAME="pgfId=9627">
</A>
getout & LB --> turnAroundState,</P>
<P CLASS="Computer">
<A NAME="pgfId=9628">
</A>
!haveAgem & GEM --> getGemState,</P>
<P CLASS="Computer">
<A NAME="pgfId=9629">
</A>
!WL --> turnLState,</P>
<P CLASS="Computer">
<A NAME="pgfId=9630">
</A>
!WF --> goFwdState,</P>
<P CLASS="Computer">
<A NAME="pgfId=9631">
</A>
!WR --> turnRState,</P>
<P CLASS="Computer">
<A NAME="pgfId=9632">
</A>
!WB --> turnAroundState;</P>
<P CLASS="Computer">
<A NAME="pgfId=9633">
</A>
state goFwdState --> MF searchState;</P>
<P CLASS="Computer">
<A NAME="pgfId=9635">
</A>
state turnLState --> TA goFwdState;</P>
<P CLASS="Computer">
<A NAME="pgfId=9637">
</A>
state turnRState --> TC goFwdState;</P>
<P CLASS="Computer">
<A NAME="pgfId=9639">
</A>
state turnAroundState --> TC turnAgainState;</P>
<P CLASS="Computer">
<A NAME="pgfId=104751">
</A>
state ejectState --> THROWUP !haveAgem searchState;</P>
<P CLASS="Computer">
<A NAME="pgfId=104752">
</A>
state jumpState --> SHUTUP shutdownState;</P>
<P CLASS="Computer">
<A NAME="pgfId=104753">
</A>
state getGemState --> PICKUP haveAgem searchState;</P>
<P CLASS="Computer">
<A NAME="pgfId=9647">
</A>
state shutDownState --> SHUTUP shutDownState;</P>
<P CLASS="Computer">
<A NAME="pgfId=9649">
</A>
state turnAgainState --> TC searchState;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=9651">
</A>
end</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=9654">
</A>
a. (120 min.) Draw Jim’s state machine diagram and translate it to an HDL. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=26947">
</A>
b. (120 min.) Build a model for the maze that will work with Jim’s design.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=26948">
</A>
c. (120 min.) Simulate the operation of Jim’s beetle using your maze model.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=26949">
</A>
d. (Hours) Can you do better than Jim?</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=10132">
</A>
13.22 <A NAME="13744">
</A>
(Switch-level simulation, 120 min.) Perform the switch-level simulation shown in <A HREF="CH13.9.htm#29188" CLASS="XRef">
Section 13.9</A>
.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=96867">
</A>
13.23 (**Simulation, 60 min.) (From a question posed by Ray Ryan to the VITAL timing group.) Suppose we have a two-input NAND gate (inputs I1 and I2, and output Q) with separate path delays from I1 to Q and from I2 to Q with delays as follows:</P>
<P CLASS="Computer">
<A NAME="pgfId=10845">
</A>
tpd_I1_Q => </P>
<P CLASS="Computer">
<A NAME="pgfId=10137">
</A>
( tr01 => 10 ns, -- falling I1 -> rising Q</P>
<P CLASS="Computer">
<A NAME="pgfId=9914">
</A>
tr10 => 7 ns ) -- rising I1 -> falling Q</P>
<P CLASS="Computer">
<A NAME="pgfId=9915">
</A>
tpd_I2_Q =></P>
<P CLASS="Computer">
<A NAME="pgfId=10138">
</A>
( tr01 => 5 ns, -- falling I2 -> rising Q</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=9916">
</A>
tr10 => 3 ns ) -- rising I1 -> falling Q</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=9919">
</A>
a. For inputs: (I1:0->1, 9 ns; I2:0->1, 10 ns), should Q fall at:</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=10217">
</A>
12 ns, 13 ns, 16 ns, 17 ns or other?</P>
<UL>
<LI CLASS="ExercisePart">
<A NAME="pgfId=9937">
</A>
b. For inputs: (I2:0->1, 9 ns; I1:0->1, 10 ns), should Q fall at:</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=9948">
</A>
12 ns, 13 ns, 16 ns, 17 ns or other?</P>
<UL>
<LI CLASS="ExercisePart">
<A NAME="pgfId=9955">
</A>
c. For inputs: (I2:0->1, 10 ns; I1:0->1, 10 ns), should Q fall at:</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=9966">
</A>
13 ns, 15 ns, 17 ns, 20 ns or other?</P>
<UL>
<LI CLASS="ExercisePart">
<A NAME="pgfId=9973">
</A>
d. For inputs: (I1:1->0, 9 ns; I2:1->0, 10 ns), should Q rise at:</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=9984">
</A>
14 ns, 15 ns, 19 ns, 20 ns or other?</P>
<UL>
<LI CLASS="ExercisePart">
<A NAME="pgfId=9991">
</A>
e. For inputs: (I2:1->0, 9 ns; I1:1->0, 10 ns), should Q rise at:</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=10002">
</A>
14 ns, 15 ns, 19 ns, 20 ns or other?</P>
<UL>
<LI CLASS="ExercisePart">
<A NAME="pgfId=10009">
</A>
f. For inputs: (I1:0->1, 10 ns; I2:0->1, 10 ns), should Q fall at:</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=10719">
</A>
13 ns, 15 ns, 17 ns, 20 ns or other?</P>
<P CLASS="Exercise">
<A NAME="pgfId=10027">
</A>
In each case explain your answer using actual simulation results to help you.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=20181">
</A>
13.24 (VHDL trace, 30 min.) Write a simple testbench and trace through the following VHDL behavioral simulation. </P>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=58010">
</A>
<B CLASS="Keyword">
library</B>
IEEE; </P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=58011">
</A>
<B CLASS="Keyword">
use</B>
IEEE.std_logic_1164.<B CLASS="Keyword">
all</B>
; <B CLASS="Keyword">
use</B>
IEEE.NUMERIC_STD.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=58012">
</A>
<B CLASS="Keyword">
entity</B>
comp_mux <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=58013">
</A>
<B CLASS="Keyword">
generic</B>
(TPD : TIME := 1 ns);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=58014">
</A>
<B CLASS="Keyword">
port</B>
(A, B : <B CLASS="Keyword">
in</B>
STD_LOGIC_VECTOR (2 <B CLASS="Keyword">
downto</B>
0); </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=58015">
</A>
Y : <B CLASS="Keyword">
out</B>
STD_LOGIC_VECTOR (2 <B CLASS="Keyword">
downto</B>
0));</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=58016">
</A>
<B CLASS="Keyword">
end</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=58017">
</A>
<B CLASS="Keyword">
architecture</B>
Behave <B CLASS="Keyword">
of</B>
comp_mux <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=58018">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=58019">
</A>
Y <= A <B CLASS="Keyword">
after</B>
TPD <B CLASS="Keyword">
when</B>
(A <= B) <B CLASS="Keyword">
else</B>
B <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=58020">
</A>
<B CLASS="Keyword">
end</B>
;</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=58024">
</A>
13.25 (VHDL simulator, 30 min.) Explain the steps in using your VHDL simulator. Are there separate compile, analyze, elaborate, initialization, and simulate phases. Where and when do they occur. How do you know?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=58070">
</A>
13.26 (Debugging VHDL, 60 min.) Correct the errors in the following code:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=58071">
</A>
entity counter8 is port (</P>
<P CLASS="Computer">
<A NAME="pgfId=58072">
</A>
rset, updn, clock : in bit; carry : out bit; count : buffer integer range 0 to 255 );</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=58073">
</A>
end counter8;</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=58074">
</A>
architecture behave of counter8 is</P>
<P CLASS="Computer">
<A NAME="pgfId=58075">
</A>
begin process</P>
<P CLASS="Computer">
<A NAME="pgfId=58076">
</A>
begin</P>
<P CLASS="Computer">
<A NAME="pgfId=58077">
</A>
wait until clock'event and clock = '1';</P>
<P CLASS="Computer">
<A NAME="pgfId=58078">
</A>
if (rset = '1') then count <= 0; carry <= '0';</P>
<P CLASS="Computer">
<A NAME="pgfId=58079">
</A>
else case updn</P>
<P CLASS="Computer">
<A NAME="pgfId=58080">
</A>
when '1' => count <= count + 1;</P>
<P CLASS="Computer">
<A NAME="pgfId=58081">
</A>
if (count = 255) then carry <= '1'; else carry <= '0'; end if;</P>
<P CLASS="Computer">
<A NAME="pgfId=58082">
</A>
when '0' => count <= count - 1;</P>
<P CLASS="Computer">
<A NAME="pgfId=58083">
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