📄 ch13.c.htm
字号:
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN">
<HTML>
<HEAD>
<META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter">
<TITLE> 13.12 Problems</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
<P>[ <A HREF="CH13.htm">Chapter start</A> ] [ <A HREF="CH13.b.htm">Previous page</A> ] [ <A HREF="CH13.d.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
<H1 CLASS="Heading1">
<A NAME="pgfId=4421">
</A>
13.12 <A NAME="40459">
</A>
Problems</H1>
<P CLASS="Exercise">
<A NAME="pgfId=76127">
</A>
* = Difficult, ** = Very difficult, *** = Extremely difficult</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=80554">
</A>
13.1 (Errors, 30 min.) Change <SPAN CLASS="BodyComputer">
a <= b</SPAN>
to <SPAN CLASS="BodyComputer">
a >= b</SPAN>
in line <A HREF="CH13.2.htm#25951" CLASS="XRef">
4</A>
in module <SPAN CLASS="BodyComputer">
reference</SPAN>
in <A HREF="CH13.2.htm#23329" CLASS="XRef">
Section 13.2.1</A>
. Simulate the testbench (write models for the five logic cell models not shown in <A HREF="CH13.2.htm#23329" CLASS="XRef">
Section 13.2.1</A>
). How many errors are there, and why? <SPAN CLASS="Emphasis">
Answer: </SPAN>
56.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=97491">
</A>
13.2 (False paths, 15 min.) The following code forces an output pin to a constant value. Perform a timing analysis on this model and comment on the results.</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=97492">
</A>
<B CLASS="Keyword">
module</B>
check_critical_path_2 (a, z);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=97493">
</A>
<B CLASS="Keyword">
input</B>
a; <B CLASS="Keyword">
output</B>
z; <B CLASS="Keyword">
supply1</B>
VDD; <B CLASS="Keyword">
supply0</B>
VSS;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=97485">
</A>
nd02d0 b1_i3 (.a1(a), .a2(VSS), .zn(z)); // 2-input NAND</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=79610">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=79664">
</A>
13.3 (Timing loops, 30 min.) The following code models a <A NAME="marker=86054">
</A>
set–reset latch with feedback to implement a memory element. Perform a timing analysis on this model and comment on the results.</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=79665">
</A>
<B CLASS="Keyword">
module</B>
check_critical_path_3 (s, r, q, qn);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=79666">
</A>
<B CLASS="Keyword">
input</B>
s, r; <B CLASS="Keyword">
output</B>
q, qn; <B CLASS="Keyword">
supply1</B>
VDD; <B CLASS="Keyword">
supply0</B>
VSS;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=79668">
</A>
nr02d0 b1_i1 (.a1(s), .a2(qn), .zn(q)); // 2-input NOR</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=79669">
</A>
nr02d0 b1_i2 (.a1(r), .a2(q), .zn(qn)); // 2-input NOR</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=79670">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=79662">
</A>
13.4 (Simulation script, 30 min.) Perform a gate-level simulation of the comparator/MUX in <A HREF="CH13.2.htm#22198" CLASS="XRef">
Section 13.2.3</A>
. Write a script to set input values and so on.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=100221">
</A>
13.5 (Verilog loops, 30 min.) Change the index from <SPAN CLASS="BodyComputer">
integer</SPAN>
to <SPAN CLASS="BodyComputer">
reg</SPAN>
(width three) in each loop in <SPAN CLASS="BodyComputer">
testbench.v</SPAN>
from <A HREF="CH13.2.htm#16644" CLASS="XRef">
Section 13.2</A>
. Explain the simulation result.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=100229">
</A>
13.6 (Verilog time, 30 min.) Remove <SPAN CLASS="BodyComputer">
'#1'</SPAN>
from line <A HREF="CH13.2.htm#41922" CLASS="XRef">
15</A>
in <SPAN CLASS="BodyComputer">
testbench.v</SPAN>
from <A HREF="CH13.2.htm#16644" CLASS="XRef">
Section 13.2</A>
. Explain carefully the simulation result.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=85829">
</A>
13.7 (<A NAME="marker=86053">
</A>
Infinite loops, 30 min.) Construct an HDL program that loops infinitely on a UNIX machine (with no output file!) and explain how the following helps:</P>
<P CLASS="Computer">
<A NAME="pgfId=26436">
</A>
<293> ps</P>
<P CLASS="Computer">
<A NAME="pgfId=26437">
</A>
PID TT STAT TIME COMMAND</P>
<P CLASS="Computer">
<A NAME="pgfId=26439">
</A>
...</P>
<P CLASS="Computer">
<A NAME="pgfId=26455">
</A>
28920 p1 R 0:30 verilog infinite_loop.v</P>
<P CLASS="Computer">
<A NAME="pgfId=26443">
</A>
...</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=26458">
</A>
<294> kill -9 28920</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=32360">
</A>
13.8 (Verilog graphics, 30 min.) Experiment with graphical <A NAME="marker=86052">
</A>
waveform dumps from Verilog. For example, in VeriWell you need to include the following statement:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=32701">
</A>
<B CLASS="Keyword">
initial </B>
$dumpvars; </P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=32731">
</A>
The file Dump file <SPAN CLASS="BodyComputer">
veriwell.dmp</SPAN>
should appear. Next, select <SPAN CLASS="BodyComputer">
File...</SPAN>
, then <BR>
<SPAN CLASS="BodyComputer">
Convert Dumpvar... </SPAN>
Write a cheat sheet on how to use and display simulation results from a hierarchical model.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=32724">
</A>
13.9 <A NAME="15700">
</A>
(Unknowns, 30 min.) Explain, using truth tables, the function of primitive <SPAN CLASS="BodyComputer">
G6</SPAN>
in module <SPAN CLASS="BodyComputer">
mx21d1</SPAN>
from <A HREF="CH13.2.htm#23329" CLASS="XRef">
Section 13.2.1</A>
. <SPAN CLASS="Emphasis">
Hint:</SPAN>
Consider <A NAME="marker=86046">
</A>
unknown propagation. Eliminate primitive <SPAN CLASS="BodyComputer">
G6</SPAN>
as follows and use simulation to compare the two models:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=86007">
</A>
<B CLASS="Keyword">
not</B>
G3(N3,s); <B CLASS="Keyword">
and</B>
G4(N4,i0,N3), G5(N5,s,i1); <B CLASS="Keyword">
or</B>
G7(z,N4,N5);</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=86004">
</A>
13.10 <A NAME="14237">
</A>
(Data books, 10 min.) Explain carefully what you safely can and cannot deduce from the data book figures in <A HREF="CH13.c.htm#15273" CLASS="XRef">
Table 13.16</A>
.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=97933">
</A>
TABLE 13.16 <A NAME="15273">
</A>
Input capacitances—AOIabcd family (Problem <A HREF="CH13.c.htm#14237" CLASS="XRef">
13.10</A>
).</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=97943">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=97945">
</A>
<SPAN CLASS="TableHeads">
1X drive</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=97947">
</A>
<SPAN CLASS="TableHeads">
2X drive</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=97949">
</A>
<SPAN CLASS="TableHeads">
4X drive</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97951">
</A>
<SPAN CLASS="TableHeads">
Area</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97953">
</A>
0.034 pF</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97955">
</A>
0.069 pF</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97957">
</A>
0.138 pF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=97959">
</A>
<SPAN CLASS="TableHeads">
Performance</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97961">
</A>
0.145 pF</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97963">
</A>
0.294 pF</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=97965">
</A>
0.588 pF</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseHead">
<A NAME="pgfId=85850">
</A>
13.11 (Synthesis, 30 min.) Synthesize <SPAN CLASS="BodyComputer">
comp_mux_rrr.v</SPAN>
in <A HREF="CH13.7.htm#13759" CLASS="XRef">
Section 13.7</A>
. What type and how many sequential elements result? <SPAN CLASS="Emphasis">
Answer:</SPAN>
16.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=31475">
</A>
13.12 (Place and route, 60 min.) Route both <SPAN CLASS="BodyComputer">
comp_mux.v</SPAN>
(<A HREF="CH13.2.htm#16644" CLASS="XRef">
Section 13.2</A>
) and <SPAN CLASS="BodyComputer">
comp_mux_rrr.v</SPAN>
(<A HREF="CH13.7.htm#13759" CLASS="XRef">
Section 13.7</A>
) using an FPGA. What fraction of the chip is used? <SPAN CLASS="Emphasis">
Answer:</SPAN>
For an Actel 1415 FPGA, <SPAN CLASS="BodyComputer">
comp_mux_rrr.v</SPAN>
uses about 10 percent of the available logic.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=93287">
</A>
13.13 (Timing analysis, 60 min.) Perform timing analysis on a routed version of <SPAN CLASS="BodyComputer">
comp_mux.v</SPAN>
from <A HREF="CH13.2.htm#16644" CLASS="XRef">
Section 13.2</A>
. Use worst-case commercial conditions.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=118437">
</A>
13.14 (***NAND gate delay, 120 min.) The following example of a six-input NAND gate illustrates the difference between transistor-level and other levels of simulation. A designer once needed a delay element (do not ask why!). Looking at the data book they found a six-input NAND gate had the right delay, but they did not know what to do with the other five inputs. So they tied all six inputs together. This is a horrendous error, but why? <SPAN CLASS="Emphasis">
Hint:</SPAN>
You might have to simulate a structural model using both digital simulation and a circuit-level simulation in order to explain.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=118444">
</A>
13.15 (<A NAME="23645">
</A>
Logic systems, 30 min.) Compare the 12 value system of <A HREF="CH13.3.htm#36966" CLASS="XRef">
Table 13.5</A>
with the IEEE 1164 standard and explain: Which logic values are equivalent in both systems, which logic values have no equivalents, and why there is a difference in the number of values (12 versus 9) when both systems have the same number of logic levels and logic strengths?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=30969">
</A>
13.16 (VHDL overloaded functions, 30 min.) Write a definition for the type <SPAN CLASS="BodyComputer">
stdlogic_table</SPAN>
used in the <SPAN CLASS="BodyComputer">
and</SPAN>
function in <A HREF="CH13.3.htm#32272" CLASS="XRef">
Section 13.3.2</A>
,</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=30972">
</A>
constant and_table:stdlogic_table </P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=30987">
</A>
Compile, simulate, and test the <SPAN CLASS="BodyComputer">
and</SPAN>
function.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=11578">
</A>
13.17 <A NAME="34514">
</A>
(**Scheduling transactions in VHDL, 60 min.) (From an example in the VHDL LRM.) Consider this assignment to an integer <SPAN CLASS="BodyComputer">
S</SPAN>
in a VHDL process:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=7280">
</A>
S <= reject 15 ns inertial 12 after 20 ns, 18 after 41 ns;</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=6077">
</A>
Assume that at the time this signal assignment is executed, the driver for <SPAN CLASS="BodyComputer">
S</SPAN>
in the process has the following contents (the first entry is the current driving value):</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=6078">
</A>
1 2 2 12 5 8</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=6079">
</A>
now +3ns +12ns +13ns +20ns +42ns</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=31540">
</A>
This is called the <SPAN CLASS="Definition">
projected output waveform</SPAN>
<A NAME="marker=31583">
</A>
(times are relative to the current time). The LRM states the rule for updating a projected output waveform consists of the deletion of zero or more previously computed transactions (called old transactions) from the projected output waveform, and the addition of the new transactions, as follows:</P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=31541">
</A>
All old transactions that are projected to occur at or after the time at which the earliest new transaction is projected to occur are deleted from the projected output waveform.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=31542">
</A>
The new transactions are then appended to the projected output waveform in the order of their projected occurrence.</LI>
</OL>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=31543">
</A>
If the initial delay is inertial delay, the projected output waveform is further modified as follows:</P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=31544">
</A>
All of the new transactions are marked.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=31545">
</A>
An old transaction is marked if the time at which it is projected to occur is less than the time at which the first new transaction is projected to occur minus the pulse rejection limit.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=31546">
</A>
For each remaining unmarked, old transaction, the old transaction is marked if it immediately precedes a marked transaction and its value component is the same as that of the marked transaction.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=31547">
</A>
The transaction that determines the current value of the driver is marked.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=31548">
</A>
All unmarked transactions (all of which are old transactions) are deleted from the projected output waveform.</LI>
</OL>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=31549">
</A>
For the purposes of marking transactions, any two successive null transactions in a projected output waveform are considered to have the same value component. Using these rules compute the new projected output waveform.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=7971">
</A>
13.18 (***<SPAN CLASS="BodyComputer">
awk</SPAN>
, 120 min.) Write an <SPAN CLASS="BodyComputer">
awk</SPAN>
program with the following specification to compare two simulations:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=100322">
</A>
# program to check two files with the format:</P>
<P CLASS="Computer">
<A NAME="pgfId=100323">
</A>
# time signal value</P>
<P CLASS="Computer">
<A NAME="pgfId=100324">
</A>
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -