ch13.5.htm

介绍asci设计的一本书

<A NAME="pgfId=67973">
 </A>
)</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=67974">
 </A>
(VHDL is case insensitive, but to allow the use of an SDF file with both Verilog and VHDL we must maintain case.) As in the Verilog example in <A HREF="CH13.5.htm#20815" CLASS="XRef">
Section&nbsp;13.5.3</A>
 the logic cell delay (from the input pin of the inverter, <SPAN CLASS="BodyComputer">
i</SPAN>
, to the output pin, <SPAN CLASS="BodyComputer">
zn</SPAN>
) follows the <SPAN CLASS="BodyComputer">
IOPATH</SPAN>
 keyword. In this example there is also an interconnect delay that follows the <SPAN CLASS="BodyComputer">
PORT</SPAN>
 keyword. The interconnect delay has been placed, or lumped, at the input of the inverter. In order to include back-annotation timing using the SDF file, <SPAN CLASS="BodyComputer">
SDF_b.sdf</SPAN>
, we use a command-line switch to the simulator. In the case of MTI V-System/Plus the command is as follows:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=63455">
 </A>
&lt;msmith/MTI/vital&gt; vsim -c -sdfmax /sdf_b=SDF_b.sdf sdf_testbench</P>
<P CLASS="Computer">
<A NAME="pgfId=63456">
 </A>
...</P>
<P CLASS="Computer">
<A NAME="pgfId=63457">
 </A>
#       0 ps A=0 B=0</P>
<P CLASS="Computer">
<A NAME="pgfId=63458">
 </A>
#       0 ps A=0 B=0</P>
<P CLASS="Computer">
<A NAME="pgfId=63459">
 </A>
#    1176 ps A=0 B=1</P>
<P CLASS="Computer">
<A NAME="pgfId=63460">
 </A>
#    5000 ps A=1 B=1</P>
<P CLASS="Computer">
<A NAME="pgfId=63461">
 </A>
#    6384 ps A=1 B=0</P>
<P CLASS="Computer">
<A NAME="pgfId=63462">
 </A>
#   10000 ps A=0 B=0</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=63463">
 </A>
#   11176 ps A=0 B=1</P>
<P CLASS="Body">
<A NAME="pgfId=63464">
 </A>
We have to explain to the simulator where in the design hierarchy to apply the timing information in the SDF file. The situation is like giving someone directions &#8220;Go North on the M1 and turn left at the third intersection,&#8221; but where do we start? London or Birmingham? VHDL needs much more precise directions. Using VITAL we say we back-annotate to a <SPAN CLASS="Definition">
region</SPAN>
<A NAME="marker=68057">
 </A>
. The switch <SPAN CLASS="BodyComputer">
/sdf_b=SDF_b.sdf</SPAN>
 specifies that all instance names in the SDF file, <SPAN CLASS="BodyComputer">
SDF_b.sdf</SPAN>
, are relative to the region <SPAN CLASS="BodyComputer">
/sdf_b</SPAN>
. The region refers to instance name <SPAN CLASS="BodyComputer">
sdf_b</SPAN>
 (line <A HREF="CH13.5.htm#34309" CLASS="XRef">
9</A>
 in <SPAN CLASS="BodyComputer">
entity SDF_testbench</SPAN>
), which is an instance of component <SPAN CLASS="BodyComputer">
SDF</SPAN>
. Component <SPAN CLASS="BodyComputer">
SDF</SPAN>
 in turn contains an instance of a component, <SPAN CLASS="BodyComputer">
in01d1</SPAN>
, with instance name <SPAN CLASS="BodyComputer">
i1</SPAN>
 (line <A HREF="CH13.5.htm#20214" CLASS="XRef">
7</A>
 in <SPAN CLASS="BodyComputer">
architecture SDF</SPAN>
). Through this rather (for us) difficult-to-follow set of directions, the simulator knows that</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=68104">
 </A>
... (CELL (CELLTYPE &quot;in01d1&quot;) (INSTANCE i1) ...</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=68102">
 </A>
refers to (SDF) cell or (VHDL) component <SPAN CLASS="BodyComputer">
in01d1</SPAN>
 with instance name i1 in instance <SPAN CLASS="BodyComputer">
SDF_b</SPAN>
 of the compiled model <SPAN CLASS="BodyComputer">
sdf_testbench</SPAN>
.</P>
<P CLASS="Body">
<A NAME="pgfId=68734">
 </A>
Notice that we cannot use an SDF file of the following form (as we did for the Verilog version of this example):</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=68737">
 </A>
... (CELL (CELLTYPE &quot;in01d1&quot;) (INSTANCE SDF_b.i1) ...</P>
<P CLASS="Body">
<A NAME="pgfId=68735">
 </A>
There is no instance in the VHDL model &#8220;higher&#8221; than instance name <SPAN CLASS="BodyComputer">
SDF_b </SPAN>
that we can use as a starting point for VITAL back-annotation. In the Verilog SDF file we can refer to the name of the top-level module (<SPAN CLASS="BodyComputer">
SDF_b</SPAN>
 in line <A HREF="CH13.5.htm#10786" CLASS="XRef">
2</A>
 in module <SPAN CLASS="BodyComputer">
SDF_b</SPAN>
). We cannot do this in VHDL; we must name an instance. The result is that, unless you are careful in constructing the hierarchy of your VHDL design, you may not be able to use the same SDF file for back-annotating both VHDL and Verilog.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=13590">
 </A>
13.5.6&nbsp;<A NAME="21347">
 </A>
SDF in Simulation</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=15991">
 </A>
<A NAME="marker=15990">
 </A>
SDF<A NAME="marker=90514">
 </A>
 was developed to handle back-annotation, but it is also used to describe forward-annotation of timing constraints from logic synthesis. Here is an example of an SDF file that contains the timing information for <A NAME="marker=117788">
 </A>
the halfgate ASIC design:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=67791">
 </A>
(DELAYFILE</P>
<P CLASS="Computer">
<A NAME="pgfId=67792">
 </A>
	(SDFVERSION &quot;1.0&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=67793">
 </A>
	(DESIGN &quot;halfgate_ASIC_u&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=67794">
 </A>
	(DATE &quot;Aug-13-96&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=67795">
 </A>
	(VENDOR &quot;Compass&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=67796">
 </A>
	(PROGRAM &quot;HDL Asst&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=67797">
 </A>
	(VERSION &quot;v9r1.2&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=67798">
 </A>
	(DIVIDER .)</P>
<P CLASS="Computer">
<A NAME="pgfId=67799">
 </A>
	(TIMESCALE 1 ns)</P>
<P CLASS="Computer">
<A NAME="pgfId=67800">
 </A>
	(CELL (CELLTYPE &quot;in01d0&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=67801">
 </A>
		(INSTANCE v_1.B1_i1)</P>
<P CLASS="Computer">
<A NAME="pgfId=67802">
 </A>
		(DELAY (ABSOLUTE</P>
<P CLASS="Computer">
<A NAME="pgfId=67803">
 </A>
			(IOPATH I ZN (1.151:1.151:1.151) (1.363:1.363:1.363))</P>
<P CLASS="Computer">
<A NAME="pgfId=67804">
 </A>
		))</P>
<P CLASS="Computer">
<A NAME="pgfId=67805">
 </A>
	)</P>
<P CLASS="Computer">
<A NAME="pgfId=67806">
 </A>
	(CELL (CELLTYPE &quot;pc5o06&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=67807">
 </A>
		(INSTANCE u1_2)</P>
<P CLASS="Computer">
<A NAME="pgfId=67808">
 </A>
		(DELAY (ABSOLUTE</P>
<P CLASS="Computer">
<A NAME="pgfId=67809">
 </A>
			(IOPATH I PAD (1.216:1.216:1.216) (1.249:1.249:1.249))</P>
<P CLASS="Computer">
<A NAME="pgfId=67810">
 </A>
		))</P>
<P CLASS="Computer">
<A NAME="pgfId=67811">
 </A>
	)</P>
<P CLASS="Computer">
<A NAME="pgfId=67812">
 </A>
	(CELL (CELLTYPE &quot;pc5d01r&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=67813">
 </A>
		(INSTANCE u0_2)</P>
<P CLASS="Computer">
<A NAME="pgfId=67814">
 </A>
		(DELAY (ABSOLUTE</P>
<P CLASS="Computer">
<A NAME="pgfId=67815">
 </A>
			(IOPATH PAD CIN (.169:.169:.169) (.199:.199:.199))</P>
<P CLASS="Computer">
<A NAME="pgfId=67816">
 </A>
		))</P>
<P CLASS="Computer">
<A NAME="pgfId=67817">
 </A>
	)</P>
<P CLASS="Computer">
<A NAME="pgfId=67818">
 </A>
)</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=67789">
 </A>
This SDF file describes the delay due to the input pad (cell <SPAN CLASS="BodyComputer">
pc5d01r</SPAN>
, instance name <SPAN CLASS="BodyComputer">
u0_2</SPAN>
), our inverter (cell <SPAN CLASS="BodyComputer">
in01d0</SPAN>
, instance name <SPAN CLASS="BodyComputer">
v_1.B1_i1</SPAN>
), and the output pad (cell <SPAN CLASS="BodyComputer">
pc5o06</SPAN>
, instance name <SPAN CLASS="BodyComputer">
u1_2</SPAN>
). Since this SDF file was produced before any physical layout, there are no estimates for interconnect delay. The following partial SDF file illustrates how interconnect delay can be specified in SDF.</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=15994">
 </A>
(DELAYFILE</P>
<P CLASS="Computer">
<A NAME="pgfId=16002">
 </A>
	...</P>
<P CLASS="Computer">
<A NAME="pgfId=67823">
 </A>
	(PROCESS &quot;FAST-FAST&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=16003">
 </A>
	(TEMPERATURE 0:55:100)</P>
<P CLASS="Computer">
<A NAME="pgfId=16004">
 </A>
	(TIMESCALE 100ps)</P>
<P CLASS="Computer">
<A NAME="pgfId=16005">
 </A>
(CELL (CELLTYPE &quot;CHIP&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=16006">
 </A>
	(INSTANCE TOP)</P>
<P CLASS="Computer">
<A NAME="pgfId=16007">
 </A>
	(DELAY (ABSOLUTE</P>
<P CLASS="Computer">
<A NAME="pgfId=16009">
 </A>
		(<A NAME="marker=16008">
 </A>
INTERCONNECT A.INV8.OUT B.DFF1.Q (:0.6:) (:0.6:))</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=16010">
 </A>
)))</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=16020">
 </A>
This SDF file specifies an interconnect delay (using the keyword <SPAN CLASS="BodyComputer">
INTERCONNECT</SPAN>
) of 60 ps (0.6 units with a timescale of 100 ps per unit) between the output port of an inverter with instance name <SPAN CLASS="BodyComputer">
A.INV8</SPAN>
 (note that <SPAN CLASS="BodyComputer">
'.'</SPAN>
 is the hierarchy divider) in block A and the Q input port of a D flip-flop (instance name <SPAN CLASS="BodyComputer">
B.DFF1</SPAN>
) in block B. </P>
<P CLASS="Body">
<A NAME="pgfId=16022">
 </A>
The <A NAME="marker=16021">
 </A>
triplet notation <SPAN CLASS="BodyComputer">
(min&nbsp;:&nbsp;typ&nbsp;:&nbsp;max)</SPAN>
 in SDF corresponds to minimum, typical, and maximum values of a parameter. Specifying two triplets corresponds to rising (the first triplet) and falling delays. A single triplet corresponds to both. A third triplet corresponds to turn-off delay (transitions to or from <SPAN CLASS="BodyComputer">
'Z'</SPAN>
). You can also specify six triplets (rising, falling, <SPAN CLASS="BodyComputer">
'0'</SPAN>
 to <SPAN CLASS="BodyComputer">
'Z'</SPAN>
, <SPAN CLASS="BodyComputer">
'Z'</SPAN>
 to <SPAN CLASS="BodyComputer">
'1'</SPAN>
, <SPAN CLASS="BodyComputer">
'1'</SPAN>
 to <SPAN CLASS="BodyComputer">
'Z'</SPAN>
, and <SPAN CLASS="BodyComputer">
'Z'</SPAN>
 to <SPAN CLASS="BodyComputer">
'0'</SPAN>
). When only the typical value is specified, the minimum and maximum are set equal to the typical value.</P>
<P CLASS="Body">
<A NAME="pgfId=16074">
 </A>
Logic cell delays can use several models in SDF. Here is one example:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=16060">
 </A>
	(INSTANCE B.DFF1)</P>
<P CLASS="Computer">
<A NAME="pgfId=16061">
 </A>
	(DELAY (ABSOLUTE</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=16063">
 </A>
		(<A NAME="marker=16062">
 </A>
IOPATH (POSEDGE CLK) Q (12:14:15) (11:13:15))))</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=15986">
 </A>
The <SPAN CLASS="BodyComputer">
IOPATH</SPAN>
 construct specifies a delay between the input pin and the output pin of a cell. In this example the delay is between the positive edge of the clock (input port) and the flip-flop output. </P>
<P CLASS="Body">
<A NAME="pgfId=71021">
 </A>
The following example SDF file is for an AO221 logic cell:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=6465">
 </A>
(DELAYFILE</P>
<P CLASS="Computer">
<A NAME="pgfId=6466">
 </A>
(DESIGN &quot;MYDESIGN&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=6467">
 </A>
(DATE &quot;26 AUG 1996&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=6468">
 </A>
	(VENDOR &quot;ASICS_INC&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=6469">
 </A>
	(PROGRAM &quot;SDF_GEN&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=6470">
 </A>
(VERSION &quot;3.0&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=6471">
 </A>
	(DIVIDER .)</P>
<P CLASS="Computer">
<A NAME="pgfId=6472">
 </A>
	(VOLTAGE 3.6:3.3:3.0)</P>
<P CLASS="Computer">
<A NAME="pgfId=6473">
 </A>
	(PROCESS &quot;-3.0:0.0:3.0&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=6474">
 </A>
	(TEMPERATURE 0.0:25.0:115.0)</P>
<P CLASS="Computer">
<A NAME="pgfId=6475">
 </A>
(TIMESCALE )</P>
<P CLASS="Computer">
<A NAME="pgfId=6476">
 </A>
(CELL</P>
<P CLASS="Computer">
<A NAME="pgfId=6477">
 </A>
	(CELLTYPE &quot;AOI221&quot;)</P>
<P CLASS="Computer">
<A NAME="pgfId=6478">
 </A>
	(INSTANCE X0)</P>
<P CLASS="Computer">
<A NAME="pgfId=6479">
 </A>
	(DELAY (ABSOLUTE</P>
<P CLASS="Computer">
<A NAME="pgfId=6480">
 </A>
	(IOPATH A1 Y (1.11:1.42:2.47) (1.39:1.78:3.19))</P>
<P CLASS="Computer">
<A NAME="pgfId=6481">
 </A>
	(IOPATH A2 Y (0.97:1.30:2.34) (1.53:1.94:3.50))</P>
<P CLASS="Computer">
<A NAME="pgfId=6482">
 </A>
	(IOPATH B1 Y (1.26:1.59:2.72) (1.52:2.01:3.79))</P>
<P CLASS="Computer">
<A NAME="pgfId=6483">
 </A>
	(IOPATH B2 Y (1.10:1.45:2.56) (1.66:2.18:4.10))</P>
<P CLASS="Computer">
<A NAME="pgfId=6484">
 </A>
	(IOPATH C1 Y (0.79:1.04:1.91) (1.36:1.62:2.61))</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=6489">
 </A>
))))</P>
</DIV>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="Footnote">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=120110">
 </A>
IEEE Std 1076.4-1995, &#169; 1995 IEEE. All rights reserved.</P>
</DIV>
</DIV>
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