📄 ch13.5.htm
字号:
A; in01d1 i1 (B, A);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63197">
</A>
<B CLASS="Keyword">
initial</B>
<B CLASS="Keyword">
begin</B>
A = 0; #5; A = 1; #5; A = 0; end</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63198">
</A>
<B CLASS="Keyword">
initial</B>
$monitor("T=%6g",$realtime," A=",A," B=",B);</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=63199">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=63200">
</A>
T= 0 A=0 B=x</P>
<P CLASS="Computer">
<A NAME="pgfId=63201">
</A>
T= 0.056 A=0 B=1</P>
<P CLASS="Computer">
<A NAME="pgfId=63202">
</A>
T= 5 A=1 B=1</P>
<P CLASS="Computer">
<A NAME="pgfId=63203">
</A>
T= 5.05 A=1 B=0</P>
<P CLASS="Computer">
<A NAME="pgfId=63204">
</A>
T= 10 A=0 B=0</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=63205">
</A>
T=10.056 A=0 B=1</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=63206">
</A>
In this case the simulator has used the fixed, typical timing delays (0.056 ns for the rising delay, and 0.05 ns for the falling delay—both from line <A HREF="CH13.5.htm#14132" CLASS="XRef">
12</A>
in module <SPAN CLASS="BodyComputer">
in01d1</SPAN>
). Here is an example SDF file (filename <SPAN CLASS="BodyComputer">
SDF_b.sdf</SPAN>
) containing back-annotation timing delays:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=63207">
</A>
(DELAYFILE</P>
<P CLASS="Computer">
<A NAME="pgfId=63208">
</A>
(SDFVERSION "3.0") (DESIGN "SDF.v") (DATE "Aug-13-96")</P>
<P CLASS="Computer">
<A NAME="pgfId=63209">
</A>
(VENDOR "MJSS") (PROGRAM "MJSS") (VERSION "v0")</P>
<P CLASS="Computer">
<A NAME="pgfId=63210">
</A>
(DIVIDER .) (TIMESCALE 1 ns) </P>
<P CLASS="Computer">
<A NAME="pgfId=63211">
</A>
(CELL (CELLTYPE "in01d1")</P>
<P CLASS="Computer">
<A NAME="pgfId=63212">
</A>
(INSTANCE SDF_b.i1)</P>
<P CLASS="Computer">
<A NAME="pgfId=63213">
</A>
(DELAY (ABSOLUTE</P>
<P CLASS="Computer">
<A NAME="pgfId=63214">
</A>
(IOPATH i zn (1.151:1.151:1.151) (1.363:1.363:1.363))</P>
<P CLASS="Computer">
<A NAME="pgfId=63215">
</A>
))</P>
<P CLASS="Computer">
<A NAME="pgfId=63216">
</A>
)</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=63217">
</A>
)</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=63219">
</A>
(Notice that since Verilog is case sensitive, the instance names and node names in the SDF file are also case sensitive.) This SDF file describes the path delay between input (pin <SPAN CLASS="BodyComputer">
i</SPAN>
) and output (pin <SPAN CLASS="BodyComputer">
zn</SPAN>
) as 1.151 ns (rising delay—minimum, typical, and maximum are identical in this simple example) and 1.363 ns (falling delay). These delays are calculated by a <SPAN CLASS="Definition">
delay calculator</SPAN>
. The delay calculator may be a stand-alone tool or part of the simulator. This tool calculates the delay values by using the delay parameters in the logic cell model (lines <A HREF="CH13.5.htm#23358" CLASS="XRef">
8</A>
–<A HREF="CH13.5.htm#15116" CLASS="XRef">
9</A>
in module <SPAN CLASS="BodyComputer">
in01d1</SPAN>
). </P>
<P CLASS="Body">
<A NAME="pgfId=67399">
</A>
We call a system task, <SPAN CLASS="BodyComputer">
$sdf_annotate</SPAN>
<A NAME="marker=63218">
</A>
, to perform back-annotation,</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=63220">
</A>
`timescale 1 ns / 1 ps</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63221">
</A>
<B CLASS="Keyword">
module</B>
<A NAME="10786">
</A>
SDF_b; <B CLASS="Keyword">
reg</B>
A; in01d1 i1 (B, A);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63222">
</A>
<B CLASS="Keyword">
initial</B>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63223">
</A>
$sdf_annotate ( "SDF_b.sdf", SDF_b, , "sdf_b.log", "minimum", , );</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63224">
</A>
A = 0; #5; A = 1; #5; A = 0; end</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63225">
</A>
<B CLASS="Keyword">
initial</B>
$monitor("T=%6g",$realtime," A=",A," B=",B);</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=63226">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=63227">
</A>
Here is the output (from MTI V-System/Plus) including back-annotated timing:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=63228">
</A>
T= 0 A=0 B=x</P>
<P CLASS="Computer">
<A NAME="pgfId=63229">
</A>
T= 1.151 A=0 B=1</P>
<P CLASS="Computer">
<A NAME="pgfId=63230">
</A>
T= 5 A=1 B=1</P>
<P CLASS="Computer">
<A NAME="pgfId=63231">
</A>
T= 6.363 A=1 B=0</P>
<P CLASS="Computer">
<A NAME="pgfId=63232">
</A>
T= 10 A=0 B=0</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=66024">
</A>
T=11.151 A=0 B=1</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=67432">
</A>
The delay information from the SDF file has been passed to the simulator. </P>
<P CLASS="Body">
<A NAME="pgfId=117736">
</A>
Back-annotation is not part of the IEEE 1364 Verilog standard, although many Verilog-compatible simulators do support the <SPAN CLASS="BodyComputer">
$sdf_annotate</SPAN>
system task. Many ASIC vendors require the use of Verilog to complete a back-annotated timing simulation before they will accept a design for manufacture. Used in this way Verilog is referred to as a <SPAN CLASS="Definition">
golden simulator</SPAN>
<A NAME="marker=80245">
</A>
, since an ASIC vendor uses Verilog to judge whether an ASIC design fabricated using its process will work.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=67311">
</A>
13.5.4 VHDL Models</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=67482">
</A>
Initially VHDL did not offer a standard way to perform back-annotation. Here is an example of a VHDL model for an inverter used to perform a back-annotated timing simulation using an Altera programmable ASIC:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=67313">
</A>
<B CLASS="Keyword">
library</B>
IEEE; <B CLASS="Keyword">
use</B>
IEEE.STD_LOGIC_1164.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=67314">
</A>
<B CLASS="Keyword">
library</B>
COMPASS_LIB; <B CLASS="Keyword">
use</B>
COMPASS_LIB.COMPASS_ETC.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=67315">
</A>
<B CLASS="Keyword">
entity</B>
bknot <B CLASS="Keyword">
is</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=67316">
</A>
<B CLASS="Keyword">
generic</B>
(derating : REAL := 1.0; Z1_cap : REAL := 0.000;</P>
<P CLASS="Computer">
<A NAME="pgfId=67317">
</A>
INSTANCE_NAME : STRING := "bknot");</P>
<P CLASS="Computer">
<A NAME="pgfId=67318">
</A>
<B CLASS="Keyword">
port</B>
(Z2 : <B CLASS="Keyword">
in</B>
Std_Logic; Z1 : <B CLASS="Keyword">
out</B>
STD_LOGIC);</P>
<P CLASS="Computer">
<A NAME="pgfId=67319">
</A>
<B CLASS="Keyword">
end</B>
bknot;</P>
<P CLASS="Computer">
<A NAME="pgfId=67320">
</A>
<B CLASS="Keyword">
architecture</B>
bknot <B CLASS="Keyword">
of</B>
bknot <B CLASS="Keyword">
is</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=67321">
</A>
<B CLASS="Keyword">
constant</B>
tplh_Z2_Z1 : TIME := (1.00 ns + (0.01 ns * Z1_Cap)) * derating;</P>
<P CLASS="Computer">
<A NAME="pgfId=67322">
</A>
<B CLASS="Keyword">
constant</B>
tphl_Z2_Z1 : TIME := (1.00 ns + (0.01 ns * Z1_Cap)) * derating;</P>
<P CLASS="Computer">
<A NAME="pgfId=67323">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=67324">
</A>
<B CLASS="Keyword">
process</B>
(Z2)</P>
<P CLASS="Computer">
<A NAME="pgfId=67325">
</A>
<B CLASS="Keyword">
variable</B>
int_Z1 : Std_Logic := 'U';</P>
<P CLASS="Computer">
<A NAME="pgfId=67326">
</A>
<B CLASS="Keyword">
variable</B>
tplh_Z1, tphl_Z1, Z1_delay : time := 0 ns;</P>
<P CLASS="Computer">
<A NAME="pgfId=67327">
</A>
<B CLASS="Keyword">
variable</B>
CHANGED : BOOLEAN;</P>
<P CLASS="Computer">
<A NAME="pgfId=67328">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=67329">
</A>
int_Z1 := <B CLASS="Keyword">
not</B>
(Z2);</P>
<P CLASS="Computer">
<A NAME="pgfId=67330">
</A>
<B CLASS="Keyword">
if</B>
Z2'EVENT <B CLASS="Keyword">
then</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=67331">
</A>
tplh_Z1 := tplh_Z2_Z1; tphl_Z1 := tphl_Z2_Z1;</P>
<P CLASS="Computer">
<A NAME="pgfId=67332">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
if</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=67333">
</A>
Z1_delay := F_Delay(int_Z1, tplh_Z1, tphl_Z1);</P>
<P CLASS="Computer">
<A NAME="pgfId=67334">
</A>
Z1 <= int_Z1 after Z1_delay;</P>
<P CLASS="Computer">
<A NAME="pgfId=67335">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=67336">
</A>
<B CLASS="Keyword">
end</B>
bknot;</P>
<P CLASS="Computer">
<A NAME="pgfId=67337">
</A>
<B CLASS="Keyword">
configuration</B>
bknot_CON <B CLASS="Keyword">
of</B>
bknot <B CLASS="Keyword">
is</B>
<B CLASS="Keyword">
for</B>
bknot <B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
for</B>
;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=67338">
</A>
<B CLASS="Keyword">
end</B>
bknot_CON;</P>
<P CLASS="Body">
<A NAME="pgfId=67309">
</A>
This model accepts two generic parameters: load capacitance, <SPAN CLASS="BodyComputer">
Z1_cap</SPAN>
, and a derating factor, <SPAN CLASS="BodyComputer">
derating</SPAN>
, used to adjust postlayout timing delays. The proliferation of different VHDL back-annotation techniques drove the VHDL community to develop a standard method to complete back-annotation—VITAL.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=63356">
</A>
13.5.5 <A NAME="15313">
</A>
VITAL Models</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=67773">
</A>
<A NAME="marker=67771">
</A>
VITAL is the <A NAME="marker=67772">
</A>
VHDL Initiative Toward ASIC Libraries, IEEE Std 1076.4 [<A NAME="[IEEE Std. 1076.4, 1995]">
</A>
1995].<A HREF="#pgfId=120110" CLASS="footnote">
1</A>
VITAL allows the use of sign-off quality ASIC libraries with VHDL simulators. <SPAN CLASS="Definition">
Sign-off</SPAN>
<A NAME="marker=117769">
</A>
is the transfer of a design from a customer to an ASIC vendor. If the customer has completed simulation of a design using <A NAME="marker=67774">
</A>
<SPAN CLASS="Definition">
sign-off quality</SPAN>
models from an approved cell library and a golden simulator, the customer and ASIC vendor will sign off the design (by signing a contract) and the vendor guarantees that the silicon will match the simulation.</P>
<P CLASS="Body">
<A NAME="pgfId=63374">
</A>
VITAL models, like Verilog models, may be generated from primitive models. Here is an example of a VITAL-compliant model for an inverter,</P>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=63375">
</A>
<B CLASS="Keyword">
library</B>
IEEE; <B CLASS="Keyword">
use</B>
IEEE.STD_LOGIC_1164.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=63376">
</A>
<B CLASS="Keyword">
use</B>
IEEE.VITAL_timing.<B CLASS="Keyword">
all</B>
; <B CLASS="Keyword">
use</B>
IEEE.VITAL_primitives.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=63377">
</A>
<B CLASS="Keyword">
entity</B>
IN01D1 <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=63378">
</A>
<B CLASS="Keyword">
generic </B>
( </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=63379">
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -