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<TITLE> 13.5 Cell Models</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<P>[ <A HREF="CH13.htm">Chapter start</A> ] [ <A HREF="CH13.4.htm">Previous page</A> ] [ <A HREF="CH13.6.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
<H1 CLASS="Heading1">
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13.5 <A NAME="37732">
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Cell Models</H1>
<P CLASS="BodyAfterHead">
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There are several different kinds of logic cell models:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=65198">
</A>
<SPAN CLASS="Emphasis">
Primitive models</SPAN>
, which are produced by the ASIC library company and describe the function and properties of each logic cell (NAND, D flip-flop, and so on) using primitive functions. </LI>
<LI CLASS="BulletList">
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Verilog and VHDL models that are produced by an ASIC library company from the primitive models.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=65201">
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Proprietary models produced by library companies that describe either small logic cells or larger functions such as microprocessors.</LI>
</UL>
<P CLASS="Body">
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A logic cell model is different from the cell <SPAN CLASS="Definition">
delay model,</SPAN>
<A NAME="marker=81425">
</A>
which is used to calculate the delay of the logic cell, from the <SPAN CLASS="Definition">
power model</SPAN>
<A NAME="marker=81427">
</A>
, which is used to calculate power dissipation of the logic cell, and from the interconnect <SPAN CLASS="Definition">
timing model</SPAN>
<A NAME="marker=81439">
</A>
, which is used to calculate the delays between logic cells (we return to these in <A HREF="CH13.6.htm#16413" CLASS="XRef">
Section 13.6</A>
).</P>
<DIV>
<H2 CLASS="Heading2">
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13.5.1 <A NAME="40162">
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Primitive Models</H2>
<P CLASS="BodyAfterHead">
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The following is an example of a <SPAN CLASS="Definition">
primitive model</SPAN>
<A NAME="marker=67954">
</A>
from an ASIC library company (Compass Design Automation). This particular model (for a two-input NAND cell) is complex because it is intended for a 0.35 <SPAN CLASS="Symbol">
m</SPAN>
m process and has some advanced delay modeling features. The contents are not important to an ASIC designer, but almost all of the information about a logic cell is derived from the primitive model. The designer does not normally see this primitive model; it may only be used by an ASIC library company to generate other models—Verilog or VHDL, for example.</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=65194">
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Function</P>
<P CLASS="Computer">
<A NAME="pgfId=63907">
</A>
(timingModel = oneOf("ism","pr"); powerModel = oneOf("pin"); )</P>
<P CLASS="Computer">
<A NAME="pgfId=63908">
</A>
Rec</P>
<P CLASS="Computer">
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</A>
Logic = Function (A1; A2; )Rec ZN = not (A1 AND A2); End; End;</P>
<P CLASS="Computer">
<A NAME="pgfId=63910">
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miscInfo = Rec Title = "2-Input NAND, 1X Drive"; freq_fact = 0.5;</P>
<P CLASS="Computer">
<A NAME="pgfId=63913">
</A>
tml = "nd02d1 nand 2 * zn a1 a2";</P>
<P CLASS="Computer">
<A NAME="pgfId=63914">
</A>
MaxParallel = 1; Transistors = 4; power = 0.179018;</P>
<P CLASS="Computer">
<A NAME="pgfId=63917">
</A>
Width = 4.2; Height = 12.6; productName = "stdcell35"; libraryName = "cb35sc"; End;</P>
<P CLASS="Computer">
<A NAME="pgfId=63922">
</A>
Pin = Rec</P>
<P CLASS="Computer">
<A NAME="pgfId=63923">
</A>
A1 = Rec input; cap = 0.010; doc = "Data Input"; End;</P>
<P CLASS="Computer">
<A NAME="pgfId=63924">
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A2 = Rec input; cap = 0.010; doc = "Data Input"; End;</P>
<P CLASS="Computer">
<A NAME="pgfId=63925">
</A>
ZN = Rec output; cap = 0.009; doc = "Data Output"; End; End;</P>
<P CLASS="Computer">
<A NAME="pgfId=63927">
</A>
Symbol = Select</P>
<P CLASS="Computer">
<A NAME="pgfId=63928">
</A>
timingModel</P>
<P CLASS="Computer">
<A NAME="pgfId=63929">
</A>
On pr Do Rec</P>
<P CLASS="Computer">
<A NAME="pgfId=63930">
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tA1D_fr = |( Rec prop = 0.078; ramp = 2.749; End);</P>
<P CLASS="Computer">
<A NAME="pgfId=63931">
</A>
tA1D_rf = |( Rec prop = 0.047; ramp = 2.506; End);</P>
<P CLASS="Computer">
<A NAME="pgfId=63932">
</A>
tA2D_fr = |( Rec prop = 0.063; ramp = 2.750; End);</P>
<P CLASS="Computer">
<A NAME="pgfId=63933">
</A>
tA2D_rf = |( Rec prop = 0.052; ramp = 2.507; End); End</P>
<P CLASS="Computer">
<A NAME="pgfId=63935">
</A>
On ism Do Rec</P>
<P CLASS="Computer">
<A NAME="pgfId=63936">
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tA1D_fr = |( Rec A0 = 0.0015; dA = 0.0789; D0 = -0.2828;</P>
<P CLASS="Computer">
<A NAME="pgfId=63941">
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dD = 4.6642; B = 0.6879; Z = 0.5630; End );</P>
<P CLASS="Computer">
<A NAME="pgfId=63946">
</A>
tA1D_rf = |( Rec A0 = 0.0185; dA = 0.0477; D0 = -0.1380;</P>
<P CLASS="Computer">
<A NAME="pgfId=63951">
</A>
dD = 4.0678; B = 0.5329; Z = 0.3785; End );</P>
<P CLASS="Computer">
<A NAME="pgfId=63956">
</A>
tA2D_fr = |( Rec A0 = 0.0079; dA = 0.0462; D0 = -0.2819;</P>
<P CLASS="Computer">
<A NAME="pgfId=63961">
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dD = 4.6646; B = 0.6856; Z = 0.5282; End );</P>
<P CLASS="Computer">
<A NAME="pgfId=63966">
</A>
tA2D_rf = |( Rec A0 = 0.0060; dA = 0.0464; D0 = -0.1408;</P>
<P CLASS="Computer">
<A NAME="pgfId=63971">
</A>
dD = 4.0731; B = 0.6152; Z = 0.4064; End ); End; End;</P>
<P CLASS="Computer">
<A NAME="pgfId=63978">
</A>
Delay = |( Rec from = pin.A1; to = pin.ZN;</P>
<P CLASS="Computer">
<A NAME="pgfId=63982">
</A>
edges = Rec fr = Symbol.tA1D_fr; rf = Symbol.tA1D_rf; End; End, Rec from = pin.A2; to = pin.ZN; edges = Rec fr = Symbol.tA2D_fr; rf = Symbol.tA2D_rf; End; End );</P>
<P CLASS="Computer">
<A NAME="pgfId=64554">
</A>
MaxRampTime = |( Rec check = pin.A1; riseTime = 3.000; fallTime = 3.000; End, Rec check = pin.A2; riseTime = 3.000; fallTime = 3.000; End, Rec check = pin.ZN; riseTime = 3.000; fallTime = 3.000; End );</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=64555">
</A>
DynamicPower = |( Rec rise = { ZN }; val = 0.003; End); End; End</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=67240">
</A>
This primitive model contains the following information:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=67241">
</A>
The logic cell name, the logic cell function expressed using primitive functions, and port names.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=67259">
</A>
A list of supported delay models (<SPAN CLASS="BodyComputer">
ism</SPAN>
stands for input-slope delay model, and <SPAN CLASS="BodyComputer">
pr</SPAN>
for prop–ramp delay model—see <A HREF="CH13.6.htm#16413" CLASS="XRef">
Section 13.6</A>
).</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=67262">
</A>
Miscellaneous data on the logic cell size, the number of transistors and so on—primarily for use by logic-synthesis tools and for data book generation.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=67263">
</A>
Information for power dissipation models and timing analysis.</LI>
</UL>
</DIV>
<DIV>
<H2 CLASS="Heading2">
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</A>
13.5.2 Synopsys Models</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=64895">
</A>
The ASIC library company may provide <SPAN CLASS="Definition">
vendor models</SPAN>
<A NAME="marker=67301">
</A>
in formats unique to each CAD tool company. The following is an example of a Synopsys model derived from a primitive model similar to the example in <A HREF="CH13.5.htm#40162" CLASS="XRef">
Section 13.5.1</A>
. In a Synopsys library, each logic cell is part of a large file that also contains wire-load models and other characterization information for the cell library.</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=67270">
</A>
cell (nd02d1) {</P>
<P CLASS="Computer">
<A NAME="pgfId=65052">
</A>
/* title : 2-Input NAND, 1X Drive */</P>
<P CLASS="Computer">
<A NAME="pgfId=67282">
</A>
/* pmd checksum : 'HBA7EB26C */</P>
<P CLASS="Computer">
<A NAME="pgfId=65035">
</A>
area : 1;</P>
<P CLASS="Computer">
<A NAME="pgfId=65036">
</A>
pin(a1) { direction : input; capacitance : 0.088;</P>
<P CLASS="Computer">
<A NAME="pgfId=65037">
</A>
fanout_load : 0.088; }</P>
<P CLASS="Computer">
<A NAME="pgfId=64904">
</A>
pin(a2) { direction : input; capacitance : 0.087;</P>
<P CLASS="Computer">
<A NAME="pgfId=64907">
</A>
fanout_load : 0.087; }</P>
<P CLASS="Computer">
<A NAME="pgfId=64909">
</A>
pin(zn) { direction : output; max_fanout : 1.786;</P>
<P CLASS="Computer">
<A NAME="pgfId=64976">
</A>
max_transition : 3; function : "(a1 a2)'";</P>
<P CLASS="Computer">
<A NAME="pgfId=64914">
</A>
timing() {</P>
<P CLASS="Computer">
<A NAME="pgfId=64915">
</A>
timing_sense : "negative_unate"</P>
<P CLASS="Computer">
<A NAME="pgfId=64916">
</A>
intrinsic_rise : 0.24 intrinsic_fall : 0.17</P>
<P CLASS="Computer">
<A NAME="pgfId=64918">
</A>
rise_resistance : 1.68 fall_resistance : 1.13</P>
<P CLASS="Computer">
<A NAME="pgfId=64920">
</A>
related_pin : "a1" }</P>
<P CLASS="Computer">
<A NAME="pgfId=64922">
</A>
timing() { timing_sense : "negative_unate"</P>
<P CLASS="Computer">
<A NAME="pgfId=64924">
</A>
intrinsic_rise : 0.32 intrinsic_fall : 0.18</P>
<P CLASS="Computer">
<A NAME="pgfId=64926">
</A>
rise_resistance : 1.68 fall_resistance : 1.13</P>
<P CLASS="Computer">
<A NAME="pgfId=64928">
</A>
related_pin : "a2"</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=64929">
</A>
} } } /* end of cell */</P>
<P CLASS="Body">
<A NAME="pgfId=64845">
</A>
This file contains the only information the Synopsys logic synthesizer, simulator, and other design tools use. If the information is not in this model, the tools cannot produce it. You can see that not all of the information from a primitive model is necessarily present in a vendor model.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=63175">
</A>
13.5.3 <A NAME="20815">
</A>
Verilog Models</H2>
<P CLASS="BodyAfterHead">
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</A>
The following is a Verilog model for an inverter (derived from a primitive model):</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=63177">
</A>
`celldefine </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63178">
</A>
`delay_mode_path </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63179">
</A>
`suppress_faults </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63180">
</A>
`enable_portfaults </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63181">
</A>
`timescale 1 ns / 1 ps </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63182">
</A>
<B CLASS="Keyword">
module</B>
in01d1 (zn, i); <B CLASS="Keyword">
input</B>
i; <B CLASS="Keyword">
output</B>
zn; <B CLASS="Keyword">
not</B>
G2(zn, i);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63183">
</A>
<B CLASS="Keyword">
specify</B>
<B CLASS="Keyword">
specparam</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63184">
</A>
<A NAME="23358">
</A>
InCap$i = 0.060, OutCap$zn = 0.038, MaxLoad$zn = 1.538,</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63185">
</A>
<A NAME="15116">
</A>
R_Ramp$i$zn = 0.542:0.980:1.750, F_Ramp$i$zn = 0.605:1.092:1.950;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63186">
</A>
<B CLASS="Keyword">
specparam</B>
cell_count = 1.000000; <B CLASS="Keyword">
specparam</B>
Transistors = 4 ;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63187">
</A>
<B CLASS="Keyword">
specparam</B>
Power = 1.400000; <B CLASS="Keyword">
specparam</B>
MaxLoadedRamp = 3 ;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63188">
</A>
<A NAME="14132">
</A>
(i => zn) = (0.031:0.056:0.100, 0.028:0.050:0.090); </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63189">
</A>
<B CLASS="Keyword">
endspecify</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63190">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63191">
</A>
`nosuppress_faults</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63192">
</A>
`disable_portfaults</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=63193">
</A>
`endcelldefine</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=63194">
</A>
This is very similar in form to the model for the MUX of <A HREF="CH13.2.htm#23329" CLASS="XRef">
Section 13.2.1</A>
, except that this model includes additional timing parameters (at the beginning of the <SPAN CLASS="BodyComputer">
specify</SPAN>
block). These timing parameters were omitted to simplify the model of <A HREF="CH13.2.htm#23329" CLASS="XRef">
Section 13.2.1</A>
(see <A HREF="CH13.6.htm#16413" CLASS="XRef">
Section 13.6</A>
for an explanation of their function).</P>
<P CLASS="Body">
<A NAME="pgfId=68689">
</A>
There are no standards on writing Verilog logic cell models. In the Verilog model, <SPAN CLASS="BodyComputer">
in01d1</SPAN>
, fixed delays (corresponding to zero load capacitance) are embedded in a <SPAN CLASS="BodyComputer">
specify</SPAN>
block. The parameters describing the delay equations for the timing model and other logic cell parameters (area, power-model parameters, and so on) are specified using the Verilog <SPAN CLASS="BodyComputer">
specparam</SPAN>
feature. Writing the model in this way allows the model information to be accessed using the Verilog PLI routines. It also allows us to back-annotate timing information by overriding the data in the <SPAN CLASS="BodyComputer">
specify</SPAN>
block.</P>
<P CLASS="Body">
<A NAME="pgfId=67350">
</A>
The following Verilog code tests the model for logic cell <SPAN CLASS="BodyComputer">
in01d1</SPAN>
:</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=63195">
</A>
`timescale 1 ns / 1 ps</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=63196">
</A>
<B CLASS="Keyword">
module</B>
SDF_b; <B CLASS="Keyword">
reg</B>
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