ch05.1.htm

介绍asci设计的一本书

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TABLE&nbsp;5.3&nbsp;<A NAME="41805">
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 ACT&nbsp;3 derating factors.<SUP CLASS="Superscript">
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10</A>
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Temperature T</SPAN>
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J</SUB>
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 ( junction) / &#176;C</SPAN>
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V<SUB CLASS="Subscript">
DD</SUB>
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&#8211;55</SPAN>
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&#8211;40</SPAN>
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0</SPAN>
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25</SPAN>
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70</SPAN>
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85</SPAN>
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125</SPAN>
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4.5</P>
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0.72</P>
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0.76</P>
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0.85</P>
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0.90</P>
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1.04 </P>
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1.07</P>
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1.17</P>
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 4.75</P>
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0.70</P>
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0.73</P>
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0.82</P>
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0.87</P>
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1.00</P>
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1.03</P>
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1.12</P>
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 5.00</P>
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0.68</P>
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0.71</P>
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0.79 </P>
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0.84</P>
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0.97</P>
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1.00</P>
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1.09</P>
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 5.25</P>
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0.66</P>
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0.69</P>
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0.77</P>
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0.82</P>
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0.94</P>
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0.97</P>
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1.06</P>
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5.5</P>
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0.63</P>
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0.66</P>
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0.74 </P>
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0.79 </P>
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0.90</P>
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0.93</P>
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1.01</P>
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<SPAN CLASS="Emphasis">
Source:</SPAN>
 Actel.</P>
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As an example of a timing calculation, suppose we have a Logic Module on a 'Std' speed grade A1415A (an ACT&nbsp;3 part) that drives four other Logic Modules and we wish to estimate the delay under worst-case industrial conditions. From the data in <A HREF="CH05.1.htm#42482" CLASS="XRef">
Table&nbsp;5.2</A>
 we see that the Logic Module delay for an ACT&nbsp;3 'Std' part with a fanout of four is <SPAN CLASS="EquationNumber">
t</SPAN>
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PD</SUB>
 = 5.7 ns (commercial worst-case conditions, assuming T<SUB CLASS="Subscript">
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 = T<SUB CLASS="Subscript">
A</SUB>
). </P>
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If this were the slowest path between flip-flops (very unlikely since we have only one stage of combinational logic in this path), our estimated <SPAN CLASS="Definition">
critical path delay between registers</SPAN>
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, t<SUB CLASS="Subscript">
CRIT</SUB>
, would be the combinational logic delay plus the flip-flop setup time plus the clock&#8211;output delay:</P>
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	t<SUB CLASS="Subscript">
CRIT</SUB>
 (w-c commercial) = t<SUB CLASS="Subscript">
PD</SUB>
 + t<SUB CLASS="Subscript">
SUD</SUB>
 + t<SUB CLASS="Subscript">
CO</SUB>
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	= 5.7 ns + 0.8 ns + 3.0 ns = 9.5 ns .(5.19)</P>
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(I use <A NAME="marker=106376">
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w-c<A NAME="marker=106377">
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 as an abbreviation for worst-case.) Next we need to adjust the timing to worst-case industrial conditions. The appropriate derating factor is 1.07 (from <A HREF="CH05.1.htm#41805" CLASS="XRef">
Table&nbsp;5.3</A>
); so the estimated delay is</P>
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t</SPAN>
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CRIT</SUB>
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 9.5 ns = 10.2 ns .(5.20)</P>
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Let us jump ahead a little and assume that we can calculate that T<SUB CLASS="Subscript">
J</SUB>
 = T<SUB CLASS="Subscript">
A</SUB>
 + 20 &#176;C = 105 &#176;C in our application. To find the derating factor at 105 &#176;C we linearly interpolate between the values for 85 &#176;C (1.07) and 125 &#176;C (1.17) from <A HREF="CH05.1.htm#41805" CLASS="XRef">
Table&nbsp;5.3</A>
). The interpolated derating factor is 1.12 and thus</P>
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t</SPAN>
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CRIT</SUB>
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J</SUB>
 = 105 &#176;C) = 1.12 <SPAN CLASS="Symbol">
&#165;</SPAN>
 9.5 ns = 10.6 ns ,(5.21)</P>
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giving us an operating frequency of just less than 100 MHz.</P>
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It may seem unfair to calculate the worst-case performance for the slowest speed grade under the harshest industrial conditions&#8212;but the examples in the data books are always for the fastest speed grades under less stringent commercial conditions. If we want to illustrate the use of derating, then the delays can only get worse than the data book values! The ultimate word on logic delays for all FPGAs is the timing analysis provided by the FPGA design tools. However, you should be able to calculate whether or not the answer that you get from such a tool is reasonable.</P>
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5.1.8&nbsp;Actel Logic Module Analysis</H2>
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