ch05.1.htm

介绍asci设计的一本书

, because parts are automatically sorted into plastic bins by the production tester). You pay more for the faster parts. In the case of the ACT family of FPGAs, Actel measures performance with a special <SPAN CLASS="Definition">
binning circuit</SPAN>
<A NAME="marker=28519">
 </A>
, included on every chip, that consists of an input buffer driving a string of buffers or inverters followed by an output buffer. The parts are sorted from measurements on the binning circuit according to Logic Module propagation delay. The propagation delay, <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PD</SUB>
, is defined as the average of the rising (<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PLH</SUB>
) and falling (<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PHL</SUB>
) propagation delays of a Logic Module</P>
<P CLASS="EquationNumbered">
<A NAME="pgfId=27740">
 </A>
<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PD</SUB>
 = (<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PLH</SUB>
 + <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PHL</SUB>
)/2.(5.18)</P>
<P CLASS="Body">
<A NAME="pgfId=27741">
 </A>
Since the transistor properties match so well across a chip, measurements on the binning circuit closely correlate with the speed of the rest of the Logic Modules on the die. Since the speeds of die on the same wafer also match well, most of the good die on a wafer fall into the same speed bin. <A NAME="marker=55192">
 </A>
Actel speed grades are: a 'Std' speed grade, a '1' speed grade that is approximately 15 percent faster, a '2' speed grade that is approximately 25 percent faster than 'Std', and a '3' speed grade that is approximately 35 percent faster than 'Std'.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=53689">
 </A>
5.1.7&nbsp;Worst-Case Timing</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=53682">
 </A>
If you use fully synchronous design techniques you only have to worry about how slow your circuit may be&#8212;not how fast. Designers thus need to know the maximum delays they may encounter, which we call the <SPAN CLASS="Definition">
worst-case timing</SPAN>
<A NAME="marker=34293">
 </A>
. Maximum delays in CMOS logic occur when operating under minimum voltage, maximum temperature, and slow&#8211;slow process conditions. (A <A NAME="marker=48481">
 </A>
slow&#8211;slow process refers to a process variation, or <SPAN CLASS="Definition">
process corner</SPAN>
<A NAME="marker=34294">
 </A>
, which results in slow <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistors and slow <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistors&#8212;we can also have <A NAME="marker=48478">
 </A>
fast&#8211;fast, <A NAME="marker=48479">
 </A>
slow&#8211;fast, and <A NAME="marker=48480">
 </A>
fast&#8211;slow process corners.) </P>
<P CLASS="Body">
<A NAME="pgfId=66626">
 </A>
Electronic equipment has to survive in a variety of environments and ASIC manufacturers offer several classes of qualification for different applications:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=69666">
 </A>
Commercial. <SPAN CLASS="EquationVariables">
VDD</SPAN>
 = 5 V  &#177;  5 %, T<SUB CLASS="Subscript">
A </SUB>
(ambient) = 0 to +70 &#176;C.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=69667">
 </A>
Industrial. <SPAN CLASS="EquationVariables">
VDD</SPAN>
 = 5 V  &#177;  10 %, T<SUB CLASS="Subscript">
A </SUB>
(ambient) = &#8211;40 to +85 &#176;C.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=69668">
 </A>
Military: <SPAN CLASS="EquationVariables">
VDD</SPAN>
 = 5 V  &#177;  10 %, T<SUB CLASS="Subscript">
C</SUB>
 (case) = &#8211;55 to +125 &#176;C.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=69661">
 </A>
Military: Standard <A NAME="marker=70389">
 </A>
MIL-STD-883C Class B.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=69677">
 </A>
Military extended: Unmanned spacecraft.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=69664">
 </A>
ASICs for commercial application are cheapest; ASICs for the Cruise missile are very, very expensive. Notice that commercial and industrial application parts are specified with respect to the <SPAN CLASS="Definition">
ambient temperature</SPAN>
<A NAME="marker=69707">
 </A>
 T<SUB CLASS="Subscript">
A</SUB>
 (room temperature or the temperature inside the box containing the ASIC). Military specifications are relative to the package <SPAN CLASS="Definition">
case temperature</SPAN>
<A NAME="marker=69711">
 </A>
, T<SUB CLASS="Subscript">
C</SUB>
. What is really important is the temperature of the transistors on the chip, the <SPAN CLASS="Definition">
junction temperature</SPAN>
<A NAME="marker=69712">
 </A>
, T<SUB CLASS="Subscript">
J</SUB>
, which is always higher than T<SUB CLASS="Subscript">
A</SUB>
 (unless we dissipate zero power). For most applications that dissipate a few hundred mW, T<SUB CLASS="Subscript">
J</SUB>
 is only 5&#8211;10 &#176;C higher than T<SUB CLASS="Subscript">
A</SUB>
. To calculate the value of T<SUB CLASS="Subscript">
J</SUB>
 we need to know the power dissipated by the chip and the thermal properties of the package&#8212;we shall return to this in Section&nbsp;6.6.1, &#8220;Power Dissipation.&#8221;</P>
<P CLASS="Body">
<A NAME="pgfId=69716">
 </A>
Manufacturers have to specify their operating conditions with respect to T<SUB CLASS="Subscript">
J</SUB>
 and not T<SUB CLASS="Subscript">
A</SUB>
, since they have no idea how much power purchasers will dissipate in their designs or which package they will use. Actel used to specify timing under nominal operating conditions: <SPAN CLASS="EquationVariables">
VDD</SPAN>
 = 5.0 V, and T<SUB CLASS="Subscript">
J</SUB>
 = 25 &#176;C. Actel and most other manufacturers now specify parameters under <SPAN CLASS="Definition">
worst-case commercial</SPAN>
<A NAME="marker=69717">
 </A>
 conditions: <SPAN CLASS="EquationVariables">
VDD</SPAN>
 = 4.75 V, and T<SUB CLASS="Subscript">
J</SUB>
 = +70 &#176;C.</P>
<P CLASS="Body">
<A NAME="pgfId=84136">
 </A>
<A HREF="CH05.1.htm#42482" CLASS="XRef">
Table&nbsp;5.2</A>
 shows the ACT&nbsp;3 commercial worst-case timing.<SUP CLASS="Superscript">
<A HREF="#pgfId=69727" CLASS="footnote">
6</A>
</SUP>
 In this table Actel has included some estimates of the variable routing delay shown in <A HREF="CH05.1.htm#17689" CLASS="XRef">
Figure&nbsp;5.5</A>
(a). These delay estimates depend on the number of gates connected to a gate output (the <A NAME="marker=69732">
 </A>
fanout). </P>
<P CLASS="Body">
<A NAME="pgfId=84138">
 </A>
When you design microelectronic systems (or design <SPAN CLASS="Emphasis">
anything</SPAN>
) you must use worst-case figures ( just as you would design a bridge for the worst-case load). To convert nominal or typical timing figures to the worst case (or best case), we use measured, or empirically derived, constants called <SPAN CLASS="Definition">
derating factors</SPAN>
<A NAME="marker=69733">
 </A>
 that are expressed either as a table or a graph. For example, <A HREF="CH05.1.htm#41805" CLASS="XRef">
Table&nbsp;5.3</A>
 shows the ACT&nbsp;3 derating factors from commercial worst-case to <A NAME="marker=69738">
 </A>
industrial worst-case and <A NAME="marker=69739">
 </A>
military worst-case conditions (assuming T<SUB CLASS="Subscript">
J</SUB>
 = T<SUB CLASS="Subscript">
A</SUB>
). The ACT&nbsp;1 and ACT&nbsp;2 derating factors are approximately the same.<SUP CLASS="Superscript">
<A HREF="#pgfId=69742" CLASS="footnote">
7</A>
</SUP>
</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="7">
<P CLASS="TableTitle">
<A NAME="pgfId=94170">
 </A>
TABLE&nbsp;5.2&nbsp;<A NAME="42482">
 </A>
 ACT&nbsp;3 timing parameters.<SUP CLASS="Superscript">
<A HREF="#pgfId=94168" CLASS="footnote">
8</A>
</SUP>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94184">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94186">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableFirst">
<A NAME="pgfId=94188">
 </A>
<SPAN CLASS="TableHeads">
Fanout</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=94198">
 </A>
<SPAN CLASS="TableHeads">
Family</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=94203">
 </A>
Delay<SUP CLASS="Superscript">
<A HREF="#pgfId=94202" CLASS="footnote">
9</A>
</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=94205">
 </A>
<SPAN CLASS="TableHeads">
1</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=94207">
 </A>
<SPAN CLASS="TableHeads">
2</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=94209">
 </A>
<SPAN CLASS="TableHeads">
3</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=94211">
 </A>
<SPAN CLASS="TableHeads">
4</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=94213">
 </A>
<SPAN CLASS="TableHeads">
8</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94215">
 </A>
ACT 3-3 (data book)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94217">
 </A>
t<SUB CLASS="Subscript">
PD</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94219">
 </A>
 2.9</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94221">
 </A>
3.2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94223">
 </A>
3.4</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94225">
 </A>
3.7</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94227">
 </A>
4.8</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94229">
 </A>
ACT3-2 (calculated)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94231">
 </A>
t<SUB CLASS="Subscript">
PD</SUB>
/0.85</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94233">
 </A>
3.41</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94235">
 </A>
3.76</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94237">
 </A>
4.00</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94239">
 </A>
4.35</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94241">
 </A>
5.65</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94243">
 </A>
ACT3-1 (calculated)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94245">
 </A>
t<SUB CLASS="Subscript">
PD</SUB>
/0.75</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94247">
 </A>
3.87</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94249">
 </A>
4.27</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94251">
 </A>
4.53</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94253">
 </A>
4.93</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94255">
 </A>
6.40</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94257">
 </A>
ACT3-Std (calculated)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94259">
 </A>
t<SUB CLASS="Subscript">
PD</SUB>
/0.65</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94261">
 </A>
4.46</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94263">
 </A>
4.92</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94265">
 </A>
5.23</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94267">
 </A>
5.69</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94269">
 </A>
7.38</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFootnote">
<A NAME="pgfId=94271">
 </A>
<SPAN CLASS="Emphasis">
Source: </SPAN>
Actel.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94273">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">