ch05.1.htm

介绍asci设计的一本书

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0, 1, 2, 3</P>
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1111</P>
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15</P>
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1</P>
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1</P>
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<A HREF="CH05.1.htm#35200" CLASS="XRef">
Figure&nbsp;5.3</A>
(a) shows how we might view a 2:1 MUX as a <SPAN CLASS="Definition">
function wheel</SPAN>
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, a three-input black box that can generate any one of the six functions of two-input variables: BUF, INV, AND-11, AND1-1, OR, AND. We can write the output of a function wheel as</P>
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	F1 = WHEEL1 (A, B).(5.9)</P>
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where I define the wheel function as follows:</P>
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	WHEEL1 (A, B) = MUX (A0, A1, SA).(5.10)</P>
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The MUX function is not unique; we shall define it as</P>
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	MUX (A0, A1, SA) = A0 &#183; SA' + A1 &#183; SA.(5.11)</P>
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The inputs (A0, A1, SA) are described using the notation</P>
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	A0, A1, SA  = {A, B, '0', '1'}(5.12)</P>
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to mean that each of the inputs (A0, A1, and SA) may be any of the values: A, B, '0', or '1'. I chose the name of the wheel function because it is rather like a dial that you set to your choice of function. <A HREF="CH05.1.htm#35200" CLASS="XRef">
Figure&nbsp;5.3</A>
(b) shows that the ACT&nbsp;1 Logic Module is a function generator built from two function wheels, a 2:1 MUX, and a two-input OR gate. </P>
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FIGURE&nbsp;5.3&nbsp;<A NAME="35200">
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The ACT&nbsp;1 Logic Module as a Boolean function generator. (a)&nbsp;A 2:1 MUX viewed as a function wheel. (b)&nbsp;The ACT&nbsp;1 Logic Module viewed as two function wheels, an OR gate, and a 2:1 MUX.</P>
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We can describe the ACT&nbsp;1 Logic Module in terms of two WHEEL functions:</P>
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	F = MUX&nbsp;[&nbsp;WHEEL1, WHEEL2, OR (S0, S1)&nbsp;](5.13)</P>
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Now, for example, to implement a two-input NAND gate, F = NAND (A, B) = (A &#183; B)', using an ACT&nbsp;1 Logic Module we first express F as the output of a 2:1 MUX. To split up F we expand it <SPAN CLASS="Emphasis">
wrt</SPAN>
 A (or <SPAN CLASS="Emphasis">
wrt</SPAN>
 B; since F is symmetric in A and B):</P>
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	F = A &#183; (B') + A' &#183; ('1')(5.14)</P>
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Thus to make a two-input NAND gate we assign WHEEL1 to implement INV (B), and WHEEL2 to implement '1'. We must also set the select input to the MUX connecting WHEEL1 and WHEEL2, S0 + S1 = A&#8212;we can do this with S0 = A, S1 = '1'.</P>
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Before we get too carried away, we need to realize that we do not have to worry about how to use Logic Modules to construct combinational logic functions&#8212;this has already been done for us. For example, if we need a two-input NAND gate, we just use a NAND gate symbol and software takes care of connecting the inputs in the right way to the Logic Module. </P>
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How did Actel design its Logic Modules? One of Actel&#8217;s engineers wrote a program that calculates how many functions of two, three, and four variables a given circuit would provide. The engineers tested many different circuits and chose the best one: a small, logically efficient circuit that implemented many functions. For example, the ACT&nbsp;1 Logic Module can implement all two-input functions, most functions with three inputs, and many with four inputs.</P>
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Apart from being able to implement a wide variety of combinational logic functions, the ACT&nbsp;1 module can implement sequential logic cells in a flexible and efficient manner. For example, you can use one ACT&nbsp;1 Logic Module for a transparent latch or two Logic Modules for a flip-flop. The use of latches rather than flip-flops does require a shift to a <A NAME="marker=40167">
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two-phase clocking scheme using two nonoverlapping clocks and two clock trees. Two-phase synchronous design using latches is efficient and fast but, to handle the timing complexities of two clocks requires changes to synthesis and simulation software that have not occurred. This means that most people still use flip-flops in their designs, and these require two Logic Modules.</P>
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5.1.4&nbsp;<A NAME="10953">
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ACT&nbsp;2 and ACT&nbsp;3 Logic Modules</H2>
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Using two ACT&nbsp;1 Logic Modules for a flip-flop also requires added interconnect and associated parasitic capacitance to connect the two Logic Modules. To produce an efficient two-module flip-flop macro we could use extra antifuses in the Logic Module to cut down on the parasitic connections. However, the extra antifuses would have an adverse impact on the performance of the Logic Module in other macros. The alternative is to use a separate flip-flop module, reducing flexibility and increasing layout complexity. In the ACT&nbsp;1 family Actel chose to use just one type of Logic Module. The ACT&nbsp;2 and ACT&nbsp;3 architectures use two different types of Logic Modules, and one of them does include the equivalent of a D flip-flop.</P>
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<A HREF="CH05.1.htm#10467" CLASS="XRef">
Figure&nbsp;5.4</A>
 shows the ACT&nbsp;2 and ACT&nbsp;3 Logic Modules. The ACT&nbsp;2 <SPAN CLASS="Definition">
C-Module </SPAN>
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is similar to the ACT&nbsp;1 Logic Module but is capable of implementing five-input logic functions. Actel calls its C-module a <SPAN CLASS="Emphasis">
combinatorial</SPAN>
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 module even though the module implements <SPAN CLASS="Emphasis">
combinational</SPAN>
 logic. John Wakerly blames <A NAME="marker=73264">
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MMI for the introduction of the term combinatorial [Wakerly, 1994, p.&nbsp;404].</P>
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The use of MUXes in the Actel Logic Modules (and in other places) can cause confusion in using and creating logic macros. For the Actel library, setting S = '0' selects input A of a two-input MUX. For other libraries setting S = '1' selects input A. This can lead to some very hard to find errors when moving schematics between libraries. Similar problems arise in flip-flops and latches with MUX inputs. A safer way to label the inputs of a two-input MUX is with '0' and '1', corresponding to the input selected when the select input is '1' or '0'. This notation can be extended to bigger MUXes, but in <A HREF="CH05.1.htm#10467" CLASS="XRef">
Figure&nbsp;5.4</A>
, does the input combination S0 = '1' and S1 = '0' select input D10 or input D01? These problems are not caused by Actel, but by failure to use the IEEE standard symbols in this area.</P>
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The <SPAN CLASS="Definition">
S-Module</SPAN>
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 (<SPAN CLASS="Definition">
sequential module</SPAN>
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) contains the same combinational function capability as the C-Module together with a <SPAN CLASS="Definition">
sequential element</SPAN>
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 that can be configured as a flip-flop. <A HREF="CH05.1.htm#10467" CLASS="XRef">
Figure&nbsp;5.4</A>
(d) shows the sequential element implementation in the ACT&nbsp;2 and ACT&nbsp;3 architectures. </P>
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FIGURE&nbsp;5.4&nbsp;<A NAME="18463">
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The Actel ACT&nbsp;2 and ACT&nbsp;3 Logic Modules. (a)&nbsp;The C-Module for combinational logic. (b)&nbsp;The ACT&nbsp;2 S-Module. (c)&nbsp;The ACT&nbsp;3 S-Module. (d)&nbsp;The equivalent circuit (without buffering) of the SE (sequential element). (e)&nbsp;The sequential element configured as a positive-edge&#8211;triggered D flip-flop. (Source: Actel.)</P>
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5.1.5&nbsp;Timing Model and Critical Path</H2>
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<A HREF="CH05.1.htm#17689" CLASS="XRef">
Figure&nbsp;5.5</A>
(a) shows the <SPAN CLASS="Definition">
timing model</SPAN>
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 for the ACT family.<SUP CLASS="Superscript">
<A HREF="#pgfId=67075" CLASS="footnote">
5</A>
</SUP>
 This is a simple timing model since it deals only with logic buried inside a chip and allows us only to estimate delays. We cannot predict the exact delays on an Actel chip until we have performed the place-and-route step and know how much delay is contributed by the interconnect. Since we cannot determine the exact delay before physical layout is complete, we call the Actel architecture <SPAN CLASS="Definition">
nondeterministic</SPAN>
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.</P>
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Even though we cannot determine the preroute delays exactly, it is still important to estimate the delay on a logic path. For example, <A HREF="CH05.1.htm#17689" CLASS="XRef">
Figure&nbsp;5.5</A>
(a) shows a typical situation deep inside an ASIC. Internal signal I1 may be from the output of a register (flip-flop). We then pass through some combinational logic, C1, through a register, S1, and then another register, S2. The register-to-register delay consists of a clock&#8211;Q delay, plus any combinational delay between registers, and the setup time for the next flip-flop. The speed of our system will depend on the slowest register&#8211;register delay or <SPAN CLASS="Definition">
critical path</SPAN>
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 between registers. We cannot make our clock period any longer than this or the signal will not reach the second register in time to be clocked.</P>
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<A HREF="CH05.1.htm#17689" CLASS="XRef">
Figure&nbsp;5.5</A>
(a) shows an internal logic signal, I1, that is an input to a C-module, C1. C1 is drawn in <A HREF="CH05.1.htm#17689" CLASS="XRef">
Figure&nbsp;5.5</A>
(a) as a box with a symbol comprising the overlapping letters &#8220;C&#8221; and &#8220;L&#8221; (borrowed from carpenters who use this symbol to mark the centerline on a piece of wood). We use this symbol to describe combinational logic. For the standard-speed grade ACT&nbsp;3 (we shall look at speed grading in <A HREF="CH05.1.htm#41888" CLASS="XRef">
Section&nbsp;5.1.6</A>
) the delay between the input of a C-module and the output is specified in the data book as a parameter, <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PD</SUB>
, with a maximum value of 3.0 ns. </P>
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The output of C1 is an input to an S-Module, S1, configured to implement combinational logic and a D flip-flop. The Actel data book specifies the minimum setup time for this D flip-flop as <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
SUD</SUB>
 = 0.8 ns. This means we need to get the data to the input of S1 at least 0.8 ns before the rising clock edge (for a positive-edge&#8211;triggered flip-flop). If we do this, then there is still enough time for the data to go through the combinational logic inside S1 and reach the input of the flip-flop inside S1 in time to be clocked. We can guarantee that this will work because the combinational logic delay inside S1 is fixed.</P>
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FIGURE&nbsp;5.5&nbsp;<A NAME="17689">
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The Actel ACT timing model. (a)&nbsp;Timing parameters for a 'Std' speed grade ACT&nbsp;3. (Source: Actel.) (b)&nbsp;Flip-flop timing. (c)&nbsp;An example of flip-flop timing based on ACT&nbsp;3 parameters.</P>
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The S-Module seems like good value&#8212;we get all the combinational logic functions of a C-module (with delay <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
PD</SUB>
 of 3 ns) as well as the setup time for a flip-flop for only 0.8 ns? &#8230;not really. Next I will explain why not.</P>
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<A HREF="CH05.1.htm#17689" CLASS="XRef">
Figure&nbsp;5.5</A>
(b) shows what is happening <SPAN CLASS="Emphasis">
inside</SPAN>
 an S-Module. The setup and hold times, as measured <SPAN CLASS="Emphasis">
inside</SPAN>
 (not outside) the S-Module, of the flip-flop are t'<SUB CLASS="Subscript">
SUD</SUB>
 and t'<SUB CLASS="Subscript">
H </SUB>
(a prime denotes parameters that are measured inside the S-Module). The clock&#8211;Q propagation delay is t'<SUB CLASS="Subscript">
CO</SUB>
. The parameters t'<SUB CLASS="Subscript">
SUD</SUB>
, t'<SUB CLASS="Subscript">
H</SUB>
, and t'<SUB CLASS="Subscript">
CO</SUB>
 are measured using the <SPAN CLASS="Emphasis">
internal</SPAN>
 clock signal CLKi. The propagation delay of the combinational logic <SPAN CLASS="Emphasis">
inside</SPAN>
 the S-Module is t'<SUB CLASS="Subscript">
PD</SUB>
. The delay of the combinational logic that drives the flip-flop clock signal (<A HREF="CH05.1.htm#18463" CLASS="XRef">
Figure&nbsp;5.4</A>
d) is t'<SUB CLASS="Subscript">
CLKD</SUB>
.</P>
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From <SPAN CLASS="Emphasis">
outside</SPAN>
 the S-Module, with reference to the outside clock signal CLK1:</P>
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	<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
SUD</SUB>
 = t'<SUB CLASS="Subscript">
SUD</SUB>
 + (t'<SUB CLASS="Subscript">
PD</SUB>
 &#8211; t'<SUB CLASS="Subscript">
CLKD</SUB>
),</P>
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	<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
H</SUB>
 = t'<SUB CLASS="Subscript">
H</SUB>
 + (t'<SUB CLASS="Subscript">
PD</SUB>
 &#8211; t'<SUB CLASS="Subscript">
CLKD</SUB>
),</P>
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	<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
CO</SUB>
 = t'<SUB CLASS="Subscript">
CO</SUB>
 + t'<SUB CLASS="Subscript">
CLKD</SUB>
 .(5.15)</P>
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<A HREF="CH05.1.htm#17689" CLASS="XRef">
Figure&nbsp;5.5</A>
(c) shows an example of flip-flop timing. We have no way of knowing what the <SPAN CLASS="Emphasis">
internal</SPAN>
 flip-flop parameters t'<SUB CLASS="Subscript">
SUD</SUB>
, t'<SUB CLASS="Subscript">
H</SUB>
, and t'<SUB CLASS="Subscript">
CO</SUB>
 actually are, but we can assume some reasonable values (just for illustration purposes):</P>
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	t'<SUB CLASS="Subscript">
SUD</SUB>
 = 0.4 ns, t'<SUB CLASS="Subscript">
H</SUB>
 = 0.1 ns, t'<SUB CLASS="Subscript">
CO</SUB>
 = 0.4 ns.(5.16)</P>
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We do know the delay, t'<SUB CLASS="Subscript">
PD</SUB>
, of the combinational logic inside the S-Module. It is exactly the same as the C-Module delay, so t'<SUB CLASS="Subscript">
PD</SUB>
 = 3 ns for the ACT&nbsp;3. We do not know t'<SUB CLASS="Subscript">
CLKD</SUB>
; we shall assume a reasonable value of t'<SUB CLASS="Subscript">
CLKD</SUB>
 = 2.6 ns (the exact value does not matter in the following argument).</P>
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Next we calculate the <SPAN CLASS="Emphasis">
external</SPAN>
 S-Module parameters from Eq.&nbsp;<A HREF="CH05.1.htm#35558" CLASS="XRef">
5.15</A>
 as follows:</P>
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	<SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
SUD</SUB>
 = 0.8 ns, <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
H</SUB>
 = 0.5 ns, <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
CO</SUB>
 = 3.0 ns.(5.17)</P>
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These are the same as the ACT&nbsp;3 S-Module parameters shown in <A HREF="CH05.1.htm#17689" CLASS="XRef">
Figure&nbsp;5.5</A>
(a), and I chose t'<SUB CLASS="Subscript">
CLKD</SUB>
 and the values in Eq.&nbsp;<A HREF="CH05.1.htm#23882" CLASS="XRef">
5.16</A>
 so that they would be the same. So now we see where the combinational logic delay of 3.0 ns has gone: 0.4 ns went into increasing the setup time and 2.6 ns went into increasing the clock&#8211;output delay, <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
CO</SUB>
.</P>
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From the outside we can say that the combinational logic delay is <SPAN CLASS="Emphasis">
buried</SPAN>
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 in the flip-flop setup time. FPGA vendors will point this out as an advantage that they have. Of course, we are not getting something for nothing here. It is like borrowing money&#8212;you have to pay it back.</P>
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5.1.6&nbsp;<A NAME="41888">
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Speed Grading</H2>
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Most FPGA vendors sort chips according to their speed (<A NAME="marker=28512">
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the sorting is known as<SPAN CLASS="Definition">
 speed grading</SPAN>
 or <A NAME="marker=28513">
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<SPAN CLASS="Definition">
speed binning</SPAN>