ch05.4.htm

介绍asci设计的一本书

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Another common feature in complex PLDs, also used in some PLDs, is shown in <A HREF="CH05.4.htm#13458" CLASS="XRef">
Figure&nbsp;5.13</A>
. Programming one input of the XOR gate at the macrocell output allows you to choose whether or not to invert the output (a '1' for inversion or to a '0' for no inversion). This <SPAN CLASS="Definition">
programmable inversion</SPAN>
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 can reduce the required number of product terms by using a <A NAME="marker=38145">
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de Morgan equivalent representation instead of a conventional sum-of-products form, as shown in <A HREF="CH05.4.htm#38723" CLASS="XRef">
Figure&nbsp;5.14</A>
. </P>
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As an example of using programmable inversion, consider the function</P>
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	F = A &#183; B' + A &#183; C' + A &#183; D' + A' &#183; C &#183; D&nbsp;,(5.24)</P>
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which requires four product terms&#8212;one too many for a three-wide OR array.</P>
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If we generate the complement of F instead,</P>
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	F ' = A &#183; B &#183; C &#183; D + A' &#183; D' + A' &#183; C'&nbsp;,(5.25)</P>
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this has only three product terms. To create F we invert F ', using programmable inversion.</P>
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<A HREF="CH05.4.htm#42342" CLASS="XRef">
Figure&nbsp;5.15</A>
 shows an Altera MAX macrocell and illustrates the architectures of several different product families. The implementation details vary among the families, but the basic features: wide programmable-AND array, narrow fixed-OR array, logic expanders, and programmable inversion&#8212;are very similar.<SUP CLASS="Superscript">
<A HREF="#pgfId=74005" CLASS="footnote">
1</A>
</SUP>
 Each family has the following individual characteristics:</P>
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A typical MAX 5000 chip has: 8 dedicated inputs (with both true and complement forms); 24 inputs from the chipwide interconnect (true and complement); and either 32 or 64 shared expander terms (single polarity). The MAX 5000 LAB looks like a <A NAME="marker=74006">
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32V16 PLD (ignoring the expander terms). </LI>
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The MAX 7000 LAB has 36 inputs from the chipwide interconnect and 16 shared expander terms; the MAX 7000 LAB looks like a <A NAME="marker=74007">
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36V16 PLD. </LI>
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The MAX 9000 LAB has 33 inputs from the chipwide interconnect and 16 local feedback inputs (as well as 16 shared expander terms); the MAX 9000 LAB looks like a <A NAME="marker=74008">
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49V16 PLD.  </LI>
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FIGURE&nbsp;5.15&nbsp;<A NAME="42342">
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The Altera MAX architecture. (a)&nbsp;Organization of logic and interconnect. (b)&nbsp;A MAX family LAB (Logic Array Block). (c)&nbsp;A MAX family macrocell. The macrocell details vary between the MAX families&#8212;the functions shown here are closest to those of the MAX 9000 family macrocells.</P>
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FIGURE&nbsp;5.16&nbsp;<A NAME="36397">
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The timing model for the Altera MAX architecture. (a)&nbsp; A direct path through the logic array and a register. (b) Timing for the direct path. (c)&nbsp;Using a parallel expander. (d)&nbsp;Parallel expander timing. (e)&nbsp;Making two passes through the logic array to use a shared expander. (f)&nbsp;Timing for the shared expander (there is no register in this path). All timing values are in nanoseconds for the MAX 9000 series, '15' speed grade. (<SPAN CLASS="Emphasis">
Source:</SPAN>
 Altera.)</P>
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5.4.2&nbsp;Timing Model</H2>
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<A HREF="CH05.4.htm#36397" CLASS="XRef">
Figure&nbsp;5.16</A>
 shows the Altera MAX timing model for local signals.<SUP CLASS="Superscript">
<A HREF="#pgfId=87885" CLASS="footnote">
2</A>
</SUP>
 For example, in <A HREF="CH05.4.htm#36397" CLASS="XRef">
Figure&nbsp;5.16</A>
(a) an internal signal, I1, enters the local array (the LAB interconnect with a fixed delay <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
1</SUB>
 = t<SUB CLASS="Subscript">
LOCAL</SUB>
 = 0.5 ns), passes through the AND array (delay <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
2</SUB>
 = t<SUB CLASS="Subscript">
LAD</SUB>
 = 4.0 ns), and to the macrocell flip-flop (with <SPAN CLASS="EquationNumber">
setup</SPAN>
 time, <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
3</SUB>
 = t<SUB CLASS="Subscript">
SU</SUB>
 = 3.0 ns, and clock&#8211;Q or <SPAN CLASS="Definition">
register delay</SPAN>
<A NAME="marker=53567">
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, <SPAN CLASS="EquationNumber">
t</SPAN>
<SUB CLASS="Subscript">
4</SUB>
 = t<SUB CLASS="Subscript">
RD</SUB>
= 1.0 ns). The path delay is thus: 0.5 + 4 +3 + 1 = 8.5 ns.</P>
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<A HREF="CH05.4.htm#36397" CLASS="XRef">
Figure&nbsp;5.16</A>
(c) illustrates the use of a <A NAME="marker=83476">
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<SPAN CLASS="Definition">
parallel logic expander</SPAN>
. This is different from the case of the <SPAN CLASS="Emphasis">
shared</SPAN>
 expander (<A HREF="CH05.4.htm#13458" CLASS="XRef">
Figure&nbsp;5.13</A>
), which required two passes in series through the product-term array. Using a parallel logic expander, the extra product term is generated in an adjacent macrocell in parallel with other product terms (not in series&#8212;as in a shared expander).</P>
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We can illustrate the difference between a parallel expander and a shared expander using an example function that we have used before (Eq.&nbsp;<A HREF="CH05.4.htm#11180" CLASS="XRef">
5.22</A>
),</P>
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	F = A' &#183; C &#183; D + B' &#183; C &#183; D + A &#183; B + B &#183; C' .(5.26)</P>
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This time we shall use macrocell M1 in <A HREF="CH05.4.htm#36397" CLASS="XRef">
Figure&nbsp;5.16</A>
(d) to implement F1 equal to the sum of the first three product terms in Eq.&nbsp;<A HREF="CH05.4.htm#16819" CLASS="XRef">
5.26</A>
. We use F1 (using the parallel expander connection between adjacent macrocells shown in <A HREF="CH05.4.htm#42342" CLASS="XRef">
Figure&nbsp;5.15</A>
) as an input to macrocell M2. Now we can form F = F1 + B &#183; C' without using more than three inputs of an OR gate (the MAX&nbsp;5000 has a three-wide OR array in the macrocell, the MAX&nbsp;9000, as shown in <A HREF="CH05.4.htm#42342" CLASS="XRef">
Figure&nbsp;5.15</A>
, is capable of handling five product terms in one macrocell&#8212;but the principle is the same). The total delay is the same as before, except that we add the delay of a parallel expander, t<SUB CLASS="Subscript">
PEXP</SUB>
 = 1.0 ns. Total delay is then 8.5 + 1 = 9.5 ns.</P>
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<A HREF="CH05.4.htm#36397" CLASS="XRef">
Figure&nbsp;5.16</A>
(e) and (f) shows the use of a shared expander&#8212;similar to <A HREF="CH05.4.htm#13458" CLASS="XRef">
Figure&nbsp;5.13</A>
. </P>
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The Altera MAX macrocell is more like a PLD than the other FPGA architectures discussed here; that is why Altera calls the MAX architecture a complex PLD. This means that the MAX architecture works well in applications for which PLDs are most useful: simple, fast logic with many inputs or variables.</P>
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5.4.3&nbsp;Power Dissipation in Complex PLDs</H2>
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A programmable-AND array in any PLD built using EPROM or EEPROM transistors uses a passive pull-up (a resistor or current source), and these macrocells consume <SPAN CLASS="Definition">
static power</SPAN>
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. Altera uses a switch called the <SPAN CLASS="Definition">
Turbo Bit</SPAN>
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 to control the current in the programmable-AND array in each macrocell. For the MAX 7000, static current varies between 1.4 mA and 2.2 mA per macrocell in high-power mode (the current depends on the part&#8212;generally, but not always, the larger 7000 parts have lower operating currents) and between 0.6 mA and 0.8 mA in low-power mode. For the MAX 9000, the static current is 0.6 mA per macrocell in high-current mode and 0.3 mA in low-power mode, independent of the part size.<SUP CLASS="Superscript">
<A HREF="#pgfId=73945" CLASS="footnote">
3</A>
</SUP>
 Since there are 16 macrocells in a LAB and up to 35 LABs on the largest MAX&nbsp;9000 chip (16 <SPAN CLASS="Symbol">
&#165;</SPAN>
 35 = 560 macrocells), just the static power dissipation in low-power mode can be substantial (560 <SPAN CLASS="Symbol">
&#165;</SPAN>
 0.3 mA <SPAN CLASS="Symbol">
&#165;</SPAN>
 5 V = 840 mW). If all the macrocells are in high-power mode, the static power will double. This is the price you pay for having an (up to) 114-wide AND gate delay of a few nanoseconds (t<SUB CLASS="Subscript">
LAD</SUB>
 = 4.0 ns) in the MAX 9000. For any MAX 9000 macrocell in the low-power mode it is necessary to add a delay of between 15 ns and 20 ns to any signal path through the local interconnect and logic array (including t<SUB CLASS="Subscript">
LAD</SUB>
 and t<SUB CLASS="Subscript">
PEXP</SUB>
). </P>
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<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="Footnote">
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1.</SPAN>
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1995 data book p.&nbsp;274 (5000), p.&nbsp;160 (7000), p.&nbsp;126 (9000).</P>
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2.</SPAN>
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 March 1995 data sheet, v2.</P>
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3.</SPAN>
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1995 data book, p.&nbsp;1-47.</P>
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