📄 ch05.4.htm
字号:
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN">
<HTML>
<HEAD>
<META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter">
<TITLE> 5.4 Altera MAX</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
<P>[ <A HREF="CH05.htm">Chapter start</A> ] [ <A HREF="CH05.3.htm">Previous page</A> ] [ <A HREF="CH05.5.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
<H1 CLASS="Heading1">
<A NAME="pgfId=7303">
</A>
5.4 <A NAME="24387">
</A>
Altera MAX</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=38149">
</A>
Suppose we have a simple two-level logic circuit that implements a <A NAME="marker=35196">
</A>
sum of products as shown in <A HREF="CH05.4.htm#38576" CLASS="XRef">
Figure 5.11</A>
(a). We may redraw any two-level circuit using a regular structure (<A HREF="CH05.4.htm#38576" CLASS="XRef">
Figure 5.11</A>
b): a vector of buffers, followed by a vector of AND gates (which construct the product terms) that feed OR gates (which form the sums of the product terms). We can simplify this representation still further (<A HREF="CH05.4.htm#38576" CLASS="XRef">
Figure 5.11</A>
c), by drawing the input lines to a multiple-input AND gate as if they were one horizontal wire, which we call a <SPAN CLASS="Definition">
product-term line</SPAN>
<A NAME="marker=30889">
</A>
. A structure such as <A HREF="CH05.4.htm#38576" CLASS="XRef">
Figure 5.11</A>
(c) is called <SPAN CLASS="Definition">
programmable array logic</SPAN>
<A NAME="marker=73815">
</A>
, first introduced by Monolithic Memories as the PAL series of devices. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=31308">
</A>
<IMG SRC="CH05-11.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=31311">
</A>
FIGURE 5.11 <A NAME="38576">
</A>
Logic arrays. (a) Two-level logic. (b) Organized sum of products. (c) A programmable-AND plane. (d) EPROM logic array. (e) Wired logic. </P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=73531">
</A>
Because the arrangement of <A HREF="CH05.4.htm#38576" CLASS="XRef">
Figure 5.11</A>
(c) is very similar to a ROM, we sometimes call a horizontal product-term line, which would be the bit output from a ROM, the <SPAN CLASS="Definition">
bit line</SPAN>
<A NAME="marker=73542">
</A>
. The vertical input line is the <SPAN CLASS="Definition">
word line</SPAN>
<A NAME="marker=73543">
</A>
. <A HREF="CH05.4.htm#38576" CLASS="XRef">
Figure 5.11</A>
(d) and (e) show how to build the <SPAN CLASS="Definition">
programmable-AND array</SPAN>
<A NAME="marker=48580">
</A>
(or <A NAME="marker=53213">
</A>
product-term array) from EPROM transistors. The horizontal product-term lines connect to the vertical input lines using the EPROM transistors as pull-downs at each possible connection. Applying a '1' to the gate of an unprogrammed EPROM transistor pulls the product-term line low to a '0'. A programmed <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor has a threshold voltage higher than <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="Subscript">
DD</SUB>
and is therefore always <SPAN CLASS="Emphasis">
off</SPAN>
. Thus a programmed transistor has no effect on the product-term line.</P>
<P CLASS="Body">
<A NAME="pgfId=30935">
</A>
Notice that connecting the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel EPROM transistors to a <SPAN CLASS="Definition">
pull-up resistor</SPAN>
<A NAME="marker=73926">
</A>
as shown in <A HREF="CH05.4.htm#38576" CLASS="XRef">
Figure 5.11</A>
(e) produces a <SPAN CLASS="Definition">
wired-logic</SPAN>
<A NAME="marker=48183">
</A>
function—the output is high only if all of the outputs are high, resulting in a <SPAN CLASS="Definition">
wired-AND</SPAN>
<A NAME="marker=74229">
</A>
function of the outputs. The product-term line is low when any of the inputs are high. Thus, to convert the wired-logic array into a programmable-AND array, we need to invert the sense of the inputs. We often conveniently omit these details when we draw the schematics of logic arrays, usually implemented as <A NAME="marker=35198">
</A>
NOR–NOR arrays (so we need to invert the outputs as well). They are not minor details when you implement the layout, however.</P>
<P CLASS="Body">
<A NAME="pgfId=30805">
</A>
<A HREF="CH05.4.htm#30355" CLASS="XRef">
Figure 5.12</A>
shows how a programmable-AND array can be combined with other logic into a <SPAN CLASS="Definition">
macrocell</SPAN>
<A NAME="marker=73821">
</A>
that contains a flip-flop. For example, the widely used <SPAN CLASS="Definition">
22V10</SPAN>
<A NAME="marker=30996">
</A>
PLD, also called a <A NAME="marker=35197">
</A>
registered PAL, essentially contains 10 of the macrocells shown in <A HREF="CH05.4.htm#30355" CLASS="XRef">
Figure 5.12</A>
. The part number, 22V10, denotes that there are 22 inputs (44 vertical input lines for both true and complement forms of the inputs) to the programmable AND array and 10 macrocells. The PLD or registered PAL shown in <A HREF="CH05.4.htm#30355" CLASS="XRef">
Figure 5.12</A>
has an 2<SPAN CLASS="EquationVariables">
i</SPAN>
<SPAN CLASS="Symbol">
¥</SPAN>
<SPAN CLASS="EquationVariables">
jk</SPAN>
programmable-AND array.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=7484">
</A>
<IMG SRC="CH05-12.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=7486">
</A>
FIGURE 5.12 <A NAME="30355">
</A>
A registered PAL with <SPAN CLASS="EquationVariables">
i</SPAN>
inputs, <SPAN CLASS="EquationVariables">
j</SPAN>
product terms, and k macrocells.</P>
</TD>
</TR>
</TABLE>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=7477">
</A>
5.4.1 Logic Expanders</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=87653">
</A>
The basic logic cell for the Altera MAX architecture, a <A NAME="marker=87652">
</A>
macrocell, is a descendant of the PAL. Using the <A NAME="marker=87657">
</A>
<SPAN CLASS="Definition">
logic expander</SPAN>
, shown in <A HREF="CH05.4.htm#13458" CLASS="XRef">
Figure 5.13</A>
to generate extra logic terms, it is possible to implement functions that require more product terms than are available in a simple PAL macrocell. As an example, consider the following function:</P>
<P CLASS="EqnNmbrdAlign">
<A NAME="pgfId=85315">
</A>
<A NAME="11180">
</A>
F = A' · C · D + B' · C · D + A · B + B · C'.(5.22)</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=85316">
</A>
This function has four product terms and thus we cannot implement F using a macrocell that has only a three-wide OR array (such as the one shown in <A HREF="CH05.4.htm#13458" CLASS="XRef">
Figure 5.13</A>
). If we rewrite F as a “sum of (products of products)” like this:</P>
<P CLASS="EquationAlign">
<A NAME="pgfId=53364">
</A>
F = (A' + B') · C · D + (A + C') · B</P>
<P CLASS="EqnNmbrdAlign">
<A NAME="pgfId=53354">
</A>
= (A · B)' (C · D) + (A' · C)' · B ;(5.23)</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=53353">
</A>
we can use logic expanders to form the <SPAN CLASS="Definition">
expander terms</SPAN>
<A NAME="marker=87732">
</A>
(A · B)' and (A' · C)' (see <A HREF="CH05.4.htm#13458" CLASS="XRef">
Figure 5.13</A>
). We can even share these extra product terms with other macrocells if we need to. We call the extra logic gates that form these shareable product terms a <A NAME="marker=53380">
</A>
<SPAN CLASS="Definition">
shared logic expander</SPAN>
, or just <A NAME="marker=53381">
</A>
<SPAN CLASS="Definition">
shared expander</SPAN>
. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=53229">
</A>
<IMG SRC="CH05-13.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=73848">
</A>
FIGURE 5.13 <A NAME="13458">
</A>
Expander logic and programmable inversion. An expander increases the number of product terms available and programmable inversion allows you to reduce the number of product terms you need.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=73591">
</A>
The disadvantage of the shared expanders is the extra logic delay incurred because of the second pass that you need to take through the product-term array. We usually do not know before the logic tools assign logic to macrocells (<SPAN CLASS="Definition">
logic assignment</SPAN>
<A NAME="marker=31343">
</A>
) whether we need to use the logic expanders. Since we cannot predict the exact timing the Altera MAX architecture is not strictly <A NAME="marker=31342">
</A>
<SPAN CLASS="Definition">
deterministic</SPAN>
. However, once we do know whether a signal has to go through the array once or twice, we can simply and accurately predict the delay. This is a very important and useful feature of the Altera MAX architecture. </P>
<P CLASS="Body">
<A NAME="pgfId=87728">
</A>
The expander terms are sometimes called <SPAN CLASS="Definition">
helper terms</SPAN>
<A NAME="marker=73597">
</A>
when you use a PAL. If you use helper terms in a 22V10, for example, you have to go out to the chip I/O pad and then back into the programmable array again, using <SPAN CLASS="Definition">
two-pass logic</SPAN>
<A NAME="marker=73616">
</A>
.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=88532">
</A>
<IMG SRC="CH05-14.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=88535">
</A>
FIGURE 5.14 <A NAME="38723">
</A>
Use of programmed inversion to simplify logic: (a) The function F = A · B' + A · C' + A · D' + A' · C · D requires four product terms (P1–P4) to implement while (b) the complement, F ' = A · B · C · D + A' · D' + A' · C' requires only three product terms (P1–P3).</P>
</TD>
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -