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<TITLE> 5.2 Xilinx LCA</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<H1 CLASS="Heading1">
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5.2 <A NAME="11902">
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Xilinx LCA</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=3722">
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Xilinx LCA (a trademark, denoting logic cell array) basic logic cells, <A NAME="marker=3718">
</A>
<SPAN CLASS="Definition">
configurable logic blocks</SPAN>
or <A NAME="marker=3721">
</A>
<SPAN CLASS="Definition">
CLBs</SPAN>
, are bigger and more complex than the Actel or QuickLogic cells. The Xilinx LCA basic logic cell is an example of a <SPAN CLASS="Definition">
coarse-grain architecture</SPAN>
<A NAME="marker=29786">
</A>
. The Xilinx CLBs contain both combinational logic and flip-flops. </P>
<DIV>
<H2 CLASS="Heading2">
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5.2.1 <A NAME="23590">
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XC3000 CLB</H2>
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The XC3000 CLB, shown in <A HREF="CH05.2.htm#15825" CLASS="XRef">
Figure 5.6</A>
, has five logic inputs (A–E), a common clock input (K), an asynchronous direct-reset input (RD), and an enable (EC). Using programmable MUXes connected to the SRAM programming cells, you can independently connect each of the two CLB outputs (X and Y) to the output of the flip-flops (QX and QY) or to the output of the combinational logic (F and G). </P>
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<A NAME="pgfId=7335">
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<IMG SRC="CH05-6.gif" ALIGN="BASELINE">
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=7339">
</A>
FIGURE 5.6 <A NAME="15825">
</A>
The Xilinx XC3000 CLB (configurable logic block). (Source: Xilinx.)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=3739">
</A>
A 32-bit <SPAN CLASS="Definition">
look-up table</SPAN>
<A NAME="marker=30759">
</A>
(<A NAME="marker=39363">
</A>
LUT<A NAME="marker=39364">
</A>
), stored in 32 bits of SRAM, provides the ability to implement combinational logic. Suppose you need to implement the function F = A · B · C · D · E (a five-input AND). You set the contents of LUT cell number 31 (with address '11111') in the 32-bit SRAM to a '1'; all the other SRAM cells are set to '0'. When you apply the input variables as an address to the 32-bit SRAM, only when ABCDE = '11111' will the output F be a '1'. This means that the CLB propagation delay is fixed, equal to the LUT access time, and independent of the logic function you implement.</P>
<P CLASS="Body">
<A NAME="pgfId=3748">
</A>
There are seven inputs for the combinational logic in the XC3000 CLB: the five CLB inputs (A–E), and the flip-flop outputs (QX and QY). There are two outputs from the LUT (F and G). Since a 32-bit LUT requires only five variables to form a unique address (32 = 2<SUP CLASS="Superscript">
5</SUP>
), there are several ways to use the LUT:</P>
<UL>
<LI CLASS="BulletList">
<A NAME="pgfId=3752">
</A>
You can use five of the seven possible inputs (A–E, QX, QY) with the entire 32-bit LUT. The CLB outputs (F and G) are then identical.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=6105">
</A>
You can split the 32-bit LUT in half to implement two functions of four variables each. You can choose four input variables from the seven inputs (A–E, QX, QY). You have to choose two of the inputs from the five CLB inputs (A–E); then one function output connects to F and the other output connects to G.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=6106">
</A>
You can split the 32-bit LUT in half, using one of the seven input variables as a select input to a 2:1 MUX that switches between F and G. This allows you to implement some functions of six and seven variables.</LI>
</UL>
</DIV>
<DIV>
<H2 CLASS="Heading2">
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5.2.2 XC4000 Logic Block</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=48927">
</A>
<A HREF="CH05.2.htm#27497" CLASS="XRef">
Figure 5.7</A>
shows the CLB used in the XC4000 series of Xilinx FPGAs. This is a fairly complicated basic logic cell containing 2 four-input LUTs that feed a three-input LUT. The XC4000 CLB also has special fast carry logic hard-wired between CLBs. MUX control logic maps four control inputs (C1–C4) into the four inputs: LUT input H1, direct in (DIN), enable clock (EC), and a set / reset control (S/R) for the flip-flops. The control inputs (C1–C4) can also be used to control the use of the F' and G' LUTs as 32 bits of SRAM.</P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=83448">
</A>
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<DIV>
<IMG SRC="CH05-7.gif">
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</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=83451">
</A>
FIGURE 5.7 <A NAME="27497">
</A>
The Xilinx XC4000 family CLB (configurable logic block). (<SPAN CLASS="Emphasis">
Source:</SPAN>
Xilinx.)</P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=49013">
</A>
5.2.3 XC5200 Logic Block</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=53151">
</A>
<A HREF="CH05.2.htm#40355" CLASS="XRef">
Figure 5.8</A>
shows the basic logic cell, a <SPAN CLASS="Definition">
Logic Cell </SPAN>
<A NAME="marker=53166">
</A>
or <A NAME="marker=53167">
</A>
<A NAME="marker=53168">
</A>
LC, used in the XC5200 family of Xilinx LCA FPGAs.<SUP CLASS="Superscript">
<A HREF="#pgfId=84358" CLASS="footnote">
1</A>
</SUP>
The LC is similar to the CLBs in the XC2000/3000/4000 CLBs, but simpler. Xilinx retained the term CLB in the XC5200 to mean a group of four LCs (LC0–LC3).</P>
<P CLASS="Body">
<A NAME="pgfId=53193">
</A>
The XC5200 LC contains a four-input LUT, a flip-flop, and MUXes to handle signal switching. The arithmetic carry logic is separate from the LUTs. A limited capability to cascade functions is provided (using the MUX labeled F5_MUX in logic cells LC0 and LC2 in <A HREF="CH05.2.htm#40355" CLASS="XRef">
Figure 5.8</A>
) to gang two LCs in parallel to provide the equivalent of a five-input LUT.</P>
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<P CLASS="TableFigure">
<A NAME="pgfId=47224">
</A>
</P>
<DIV>
<IMG SRC="CH05-8.gif">
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</TD>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=47227">
</A>
FIGURE 5.8 <A NAME="40355">
</A>
The Xilinx XC5200 family LC (Logic Cell) and CLB (configurable logic block). (Source: Xilinx.)</P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
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5.2.4 Xilinx CLB Analysis</H2>
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<A NAME="pgfId=50539">
</A>
The use of a LUT in a Xilinx CLB to implement combinational logic is both an advantage and a disadvantage. It means, for example, that an inverter is as slow as a five-input NAND. On the other hand a LUT simplifies timing of synchronous logic, simplifies the basic logic cell, and matches the Xilinx SRAM programming technology well. A LUT also provides the possibility, used in the XC4000, of using the LUT directly as SRAM. You can configure the XC4000 CLB as a memory—either two 16 <SPAN CLASS="Symbol">
¥</SPAN>
1 SRAMs or a 32 <SPAN CLASS="Symbol">
¥</SPAN>
1 SRAM, but this is expensive RAM.</P>
<P CLASS="Body">
<A NAME="pgfId=48031">
</A>
<A HREF="CH05.2.htm#27226" CLASS="XRef">
Figure 5.9</A>
shows the timing model for Xilinx LCA FPGAs.<SUP CLASS="Superscript">
<A HREF="#pgfId=66990" CLASS="footnote">
2</A>
</SUP>
Xilinx uses two speed-grade systems. The first uses the maximum guaranteed toggle rate of a CLB flip-flop measured in MHz as a suffix—so higher is faster. For example a Xilinx XC3020-125 has a toggle frequency of 125 MHz. The other Xilinx naming system (which supersedes the old scheme, since toggle frequency is rather meaningless) uses the approximate delay time of the combinational logic in a CLB in nanoseconds—so lower is faster in this case. Thus, for example, an XC4010-6 has t<SUB CLASS="Subscript">
ILO</SUB>
= 6.0 ns (the correspondence between speed grade and t<SUB CLASS="Subscript">
ILO</SUB>
is fairly accurate for the XC2000, XC4000, and XC5200 but is less accurate for the XC3000).</P>
<TABLE>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=87356">
</A>
FIGURE 5.9 <A NAME="27226">
</A>
The Xilinx LCA timing model. The paths show different uses of CLBs (configurable logic blocks). The parameters shown are for an XC5210-6. (<SPAN CLASS="Emphasis">
Source:</SPAN>
Xilinx.)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=48046">
</A>
<IMG SRC="CH05-9.gif" ALIGN="BASELINE">
</P>
</TD>
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</TABLE>
<P CLASS="Body">
<A NAME="pgfId=68986">
</A>
The inclusion of flip-flops and combinational logic inside the basic logic cell leads to efficient implementation of state machines, for example. The coarse-grain architecture of the Xilinx CLBs maximizes performance given the size of the SRAM programming technology element. As a result of the increased complexity of the basic logic cell we shall see (in Section 7.2, “Xilinx LCA”) that the routing between cells is more complex than other FPGAs that use a simpler basic logic cell. </P>
</DIV>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="Footnote">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=84358">
</A>
Xilinx decided to use Logic Cell as a trademark in 1995 rather as if IBM were to use Computer as a trademark today. Thus we should now only talk of a Xilinx Logic Cell (with capital letters) and not Xilinx logic cells.</P>
</DIV>
<DIV CLASS="footnote">
<P CLASS="Footnote">
<SPAN CLASS="footnoteNumber">
2.</SPAN>
<A NAME="pgfId=66990">
</A>
October 1995 (Version 3.0) data sheet.</P>
</DIV>
</DIV>
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