📄 ch05.5.htm
字号:
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73049">
</A>
8 Logic Elements (LE) in a Logic Array Block (LAB )</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73051">
</A>
<SPAN CLASS="TableHeads">
Logic cell contents</SPAN>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73052">
</A>
<SPAN CLASS="TableHeads">
(LUT = look-up table)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73054">
</A>
C-Module: 4:1 MUX, 2-input OR, 2-input AND. </P>
<P CLASS="TableLeft">
<A NAME="pgfId=73055">
</A>
S-Module: 4:1 MUX, 2-input OR, latch or D flip-flop.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73057">
</A>
LC has 16-bit LUT, 1 flip-flop (or latch), 4 MUXes</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73059">
</A>
16-bit LUT, <BR>
1 programmable flip-flop or latch, MUX logic for control, carry logic, cascade logic</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73061">
</A>
<SPAN CLASS="TableHeads">
Logic path delay</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73063">
</A>
Fixed</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73065">
</A>
Fixed</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73067">
</A>
Fixed with ability to<BR>
bypass FF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73069">
</A>
<SPAN CLASS="TableHeads">
Combinational<BR>
functions <BR>
per logic cell</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73071">
</A>
Most 3- and 4-input functions (total 766 macros)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73073">
</A>
One 4-input LUT per LC may be combined with adjacent LC to form 5-input LUT</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73075">
</A>
4-input LUT may be cascaded with adjacent LE</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73077">
</A>
<SPAN CLASS="TableHeads">
Flip-flop (FF)</SPAN>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73078">
</A>
<SPAN CLASS="TableHeads">
implementation</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73080">
</A>
1 D flip-flop (or latch) per S-Module; some FFs require 2 modules.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73082">
</A>
1 D flip-flop (or latch) per LC (4 per CLB)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73084">
</A>
1 D flip-flop (or latch) per LE</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73086">
</A>
<SPAN CLASS="TableHeads">
Basic logic cells <BR>
in each chip</SPAN>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73087">
</A>
<SPAN CLASS="TableHeads">
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73089">
</A>
A1415: 104 S + 96 C</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73090">
</A>
A1425: 160 S + 150 C</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73091">
</A>
A1440: 288 S + 276 C</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73092">
</A>
A1460: 432 S + 416 C</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73093">
</A>
A14100: 697 S + 680 C</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73095">
</A>
64 CLB (XC5202)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73096">
</A>
120 CLB (XC5204)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73097">
</A>
196 CLB (XC5206)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73098">
</A>
324 CLB (XC5210)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73099">
</A>
484 CLB (XC5215)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73101">
</A>
LEs:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73102">
</A>
208 (EPF8282/V/A /AV)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73103">
</A>
336 (EPF8452/A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73104">
</A>
504 (EPF8636A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73105">
</A>
672 (EPF8820/A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73106">
</A>
1008 (EPF81188/A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73107">
</A>
1296 (EPF81500/A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73108">
</A>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73109">
</A>
576 (EPF10K10)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73110">
</A>
1152 (EPF10K20) </P>
<P CLASS="TableLeft">
<A NAME="pgfId=73111">
</A>
1728 (EPF10K30)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73112">
</A>
2304 (EPF10K40)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73113">
</A>
2880 (EPF10K50) </P>
<P CLASS="TableLeft">
<A NAME="pgfId=73114">
</A>
3744 (EPF10K70) </P>
<P CLASS="TableLeft">
<A NAME="pgfId=73115">
</A>
4992 (EPF10K100)</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=73119">
</A>
TABLE 5.9 <A NAME="40602">
</A>
Logic cells used by programmable ASICs.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73127">
</A>
<SPAN CLASS="TableHeads">
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73129">
</A>
<SPAN CLASS="TableHeads">
AMD MACH 5</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73131">
</A>
<SPAN CLASS="TableHeads">
Actel 3200DX</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73133">
</A>
<SPAN CLASS="TableHeads">
Altera MAX 9000</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73135">
</A>
<SPAN CLASS="TableHeads">
Basic <BR>
logic cell</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73137">
</A>
4 PAL Blocks in a Segment, 16 macrocells in a PAL Block </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73139">
</A>
Based on ACT 2, plus D-module (decode) and dual-port SRAM</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73141">
</A>
16 macrocells in a LAB (Logic Array Block)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73143">
</A>
<SPAN CLASS="TableHeads">
Logic cell<BR>
contents</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73145">
</A>
20-bit to 32-bit wide OR array, switching logic, XOR gate, programmable flip-flop</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73147">
</A>
C-Module: 4:1 MUX, 2-input OR, 2-input AND</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73148">
</A>
S-Module: 4-input MUX, 2-input OR, latch or D flip-flop</P>
<P CLASS="TableLeft">
<A NAME="pgfId=91376">
</A>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73149">
</A>
D-module: 7-input AND, 2-input XOR</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73151">
</A>
Macrocell: 114-wide AND, 5-wide OR array, 1 flip-flop, 5 MUXes, programmable inversion. 16 shared logic expander OR terms, plus parallel logic expander.</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73716">
</A>
LAB looks like a 49V16 PLD.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73153">
</A>
<SPAN CLASS="TableHeads">
Logic path <BR>
delay</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73155">
</A>
Fixed</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73157">
</A>
Fixed</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73159">
</A>
Fixed (unless using expanders)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73161">
</A>
<SPAN CLASS="TableHeads">
Combinational functions per logic cell</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73163">
</A>
Wide input functions</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73165">
</A>
Most 3- and 4-input functions (total 766 macros)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73167">
</A>
Wide input functions with ability to share product terms</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73169">
</A>
<SPAN CLASS="TableHeads">
Flip-flop (FF)</SPAN>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73170">
</A>
<SPAN CLASS="TableHeads">
implementation</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73172">
</A>
1 D flip-flop or latch per macrocell</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73174">
</A>
1 D flip-flop or latch per S-Module; some FFs require 2 modules.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73176">
</A>
1 D flip-flop or latch per macrocell. More can be constructed in arrays.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73178">
</A>
<SPAN CLASS="TableHeads">
Basic logic cells <BR>
in each chip</SPAN>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73179">
</A>
<SPAN CLASS="TableHeads">
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73181">
</A>
128 (M5-128)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73182">
</A>
192 (M5-192)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73183">
</A>
256 (M5-256)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73184">
</A>
320 (M5-320)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73185">
</A>
384 (M5-384)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73186">
</A>
512 (M5-512)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73188">
</A>
A3265DX: 510 S + 475 C + 20 D</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73189">
</A>
A32100DX: 700 S + 662 C + 20 D + 2 kSRAM</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73190">
</A>
A32140D): 954 S + 912 C + 24 D</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73191">
</A>
A32200DX: 1 230 S + 1 184 C + 24 D + 2.5 kSRAM</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73192">
</A>
A32300DX: 1 888 S + 1 833 C + 28 D + 3kSRAM</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73193">
</A>
A32400DX: 2 526 S + 2 466 C + 28 D + 4 kSRAM</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73195">
</A>
Macrocells:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73196">
</A>
320 (EPM9320) 4 <SPAN CLASS="Symbol">
¥</SPAN>
5</P>
<P CLASS="TableLeft">
<A NAME="pgfId=91368">
</A>
LABs</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73197">
</A>
400 (EPM9400) 5 <SPAN CLASS="Symbol">
¥</SPAN>
5</P>
<P CLASS="TableLeft">
<A NAME="pgfId=91370">
</A>
LABs</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73198">
</A>
480 (EPM9480) 6 <SPAN CLASS="Symbol">
¥</SPAN>
5</P>
<P CLASS="TableLeft">
<A NAME="pgfId=91372">
</A>
LABs</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73199">
</A>
560 (EPM9560) 7 <SPAN CLASS="Symbol">
¥</SPAN>
5</P>
<P CLASS="TableLeft">
<A NAME="pgfId=91374">
</A>
LABs</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=92748">
</A>
The key points in this chapter are:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=53943">
</A>
The use of multiplexers, look-up tables, and programmable logic arrays</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=53944">
</A>
The difference between fine-grain and coarse-grain FPGA architectures</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=73986">
</A>
Worst-case timing design</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=53953">
</A>
Flip-flop timing</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=53945">
</A>
Timing models</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=73982">
</A>
Components of power dissipation in programmable ASICs</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=53956">
</A>
Deterministic and nondeterministic FPGA architectures</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=90926">
</A>
Next, in Chapter 6, we shall examine the I/O cells used by the various programmable ASIC families.</P>
<HR><P>[ <A HREF="CH05.htm">Chapter start</A> ] [ <A HREF="CH05.4.htm">Previous page</A> ] [ <A HREF="CH05.6.htm">Next page</A> ]</P></BODY>
<!--#include file="Copyright.html"--><!--#include file="footer.html"-->
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -