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</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72875">
</A>
<SPAN CLASS="TableHeads">
QuickLogic pASIC 1</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72877">
</A>
<SPAN CLASS="TableHeads">
Basic <BR>
logic cell</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72879">
</A>
16 macrocells in a LAB (Logic Array Block) except EPM5032, which has 32 macrocells in a single LAB</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72881">
</A>
9 macrocells within a FB (Functional Block), fast FBs (FFBs) omit ALU</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72883">
</A>
Logic Cell (LC)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72885">
</A>
<SPAN CLASS="TableHeads">
Logic cell <BR>
contents</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73695">
</A>
Macrocell: 64–106-wide AND, 3-wide OR array, 1 flip-flop, 2 MUXes, programmable inversion. 32–64 shared logic expander OR terms. </P>
<P CLASS="TableLeft">
<A NAME="pgfId=73696">
</A>
LAB looks like a 32V16 PLD.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72889">
</A>
Macrocell: 21-wide AND, 16-wide OR array, 1 flip-flop, 1ALU</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73687">
</A>
FB looks like 21V9 PLD.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72891">
</A>
Four 2-input and two 6-input AND, three 2:1 MUXes and one D flip-flop</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72893">
</A>
<SPAN CLASS="TableHeads">
Logic path<BR>
delay</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72895">
</A>
Fixed (unless using shared logic expanders)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72897">
</A>
Fixed</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72899">
</A>
Fixed</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72901">
</A>
<SPAN CLASS="TableHeads">
Combinational <BR>
logic functions <BR>
per logic cell</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72903">
</A>
Wide input functions with ability to share product terms</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72905">
</A>
Wide input functions with added 2-input ALU</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72907">
</A>
All 3-input functions</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72909">
</A>
<SPAN CLASS="TableHeads">
Flip-flop (FF)</SPAN>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72910">
</A>
<SPAN CLASS="TableHeads">
implementation</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72912">
</A>
1 D flip-flop or latch per macrocell. More can be constructed in arrays.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72914">
</A>
1 D flip-flop or latch per macrocell</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72916">
</A>
1 D flip-flop per LC. LCs for other flip-flops not specified.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72918">
</A>
<SPAN CLASS="TableHeads">
Basic logic cells<BR>
in each chip</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72921">
</A>
LABs:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72922">
</A>
32 (EPM5032)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72923">
</A>
64 (EPM5064)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72924">
</A>
128 (EPM5128)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72925">
</A>
128 (EPM5130)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72926">
</A>
192 (EPM5192)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72928">
</A>
FBs:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72929">
</A>
4 (XC7236A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72930">
</A>
8 (XC7272A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72931">
</A>
2 (XC7318)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72932">
</A>
4 (XC7336)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72933">
</A>
6 (XC7354)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72934">
</A>
8 (XC7372)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72935">
</A>
12 (XC73108)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72936">
</A>
16 (XC73144)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72938">
</A>
48 (QL6X8)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72939">
</A>
96 (QL8X12)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72940">
</A>
192 (QL12X16)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72941">
</A>
384 (QL16X24)</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=72945">
</A>
TABLE 5.7 <A NAME="24904">
</A>
Logic cells used by programmable ASICs.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72953">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72955">
</A>
<SPAN CLASS="TableHeads">
Crosspoint CP20K</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72957">
</A>
<SPAN CLASS="TableHeads">
Altera MAX 7k</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72959">
</A>
<SPAN CLASS="TableHeads">
Atmel AT6000</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72961">
</A>
<SPAN CLASS="TableHeads">
Basic<BR>
logic cell</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72963">
</A>
Transistor-pair tile (TPT), RAM-logic Tile (RLT)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72965">
</A>
16 macrocells in a LAB (Logic Array Block)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72967">
</A>
Cell</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72969">
</A>
<SPAN CLASS="TableHeads">
Logic cell <BR>
contents</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72971">
</A>
TPT: 2 transistors (0.5 gate). RLT: 3 inverters, two 3-input NANDs, 2-input NAND, 2-input AND.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72973">
</A>
Macrocell: wide AND, 5-wide OR array, 1 flip-flop, 3 MUXes, programmable inversion. 16 shared logic expander OR terms, plus parallel logic expander.</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73706">
</A>
LAB looks like a 36V16 PLD. </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72975">
</A>
Two 5:1 MUXes, two 4:1 MUXes, 3:1 MUX, three 2:1 MUXes, 6 pass gates, four 2-input gates, 1 D flip-flop</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72977">
</A>
<SPAN CLASS="TableHeads">
Logic path <BR>
delay</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72979">
</A>
Variable</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72981">
</A>
Fixed (unless using shared logic expanders)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72983">
</A>
Variable</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72985">
</A>
<SPAN CLASS="TableHeads">
Combinational<BR>
functions <BR>
per logic cell</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72987">
</A>
TPT is smaller than a gate, approx. 2 TPTs = 1 gate.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72989">
</A>
Wide input functions with ability to share product terms</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72991">
</A>
1-, 2-, and 3-input combinational configurations:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72992">
</A>
44 logical states and 72 physical states</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72994">
</A>
<SPAN CLASS="TableHeads">
Flip-flop (FF)</SPAN>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72995">
</A>
<SPAN CLASS="TableHeads">
implementation</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72997">
</A>
D flip-flop requires 2 RLTs and 9 TPTs</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72999">
</A>
1 D flip-flop or latch per macrocell. More can be constructed in arrays.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73001">
</A>
1 D flip-flop per cell</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73003">
</A>
<SPAN CLASS="TableHeads">
Basic logic cells <BR>
in each chip</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73006">
</A>
TPTs: </P>
<P CLASS="TableLeft">
<A NAME="pgfId=73007">
</A>
1760 (20220)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73486">
</A>
15,876 (22000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=91243">
</A>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73008">
</A>
RLTs:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73485">
</A>
440 (20220)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73487">
</A>
3969 (22000) </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73010">
</A>
Macrocells:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73011">
</A>
32 (EPM7032/V)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=92843">
</A>
64 (EPM7064)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=92844">
</A>
96 (EPM7096)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=92845">
</A>
128 (EPM70128E)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73015">
</A>
160 (EPM70160E)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73016">
</A>
192 (EPM70192E)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73017">
</A>
256 (EPM70256E)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73019">
</A>
1024 (AT6002)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73020">
</A>
1600 (AT6003)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73021">
</A>
3136 (AT6005)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=73022">
</A>
6400(AT6010)</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=73026">
</A>
TABLE 5.8 <A NAME="30912">
</A>
Logic cells used by programmable ASICs.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73034">
</A>
<SPAN CLASS="TableHeads">
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73036">
</A>
<SPAN CLASS="TableHeads">
Actel ACT 3</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73038">
</A>
<SPAN CLASS="TableHeads">
Xilinx XC5200</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73040">
</A>
<SPAN CLASS="TableHeads">
Altera FLEX 8000/10k</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73042">
</A>
<SPAN CLASS="TableHeads">
Basic <BR>
logic cell</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73044">
</A>
2 types of Logic </P>
<P CLASS="TableLeft">
<A NAME="pgfId=83358">
</A>
Module: C-Module and </P>
<P CLASS="TableLeft">
<A NAME="pgfId=83361">
</A>
S-Module (similar but not identical to ACT 2)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=73047">
</A>
4 Logic Cells (LC) in a CLB (Configurable Logic Block)</P>
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