📄 ch05.5.htm
字号:
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN">
<HTML>
<HEAD>
<META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter">
<TITLE> 5.5 Summary</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
<P>[ <A HREF="CH05.htm">Chapter start</A> ] [ <A HREF="CH05.4.htm">Previous page</A> ] [ <A HREF="CH05.6.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
<H1 CLASS="Heading1">
<A NAME="pgfId=23100">
</A>
5.5 <A NAME="10372">
</A>
Summary</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=72703">
</A>
<A HREF="CH05.5.htm#38399" CLASS="XRef">
Table 5.4</A>
is a look-up table to Tables <A HREF="CH05.5.htm#29099" CLASS="XRef">
5.5</A>
–<A HREF="CH05.5.htm#40602" CLASS="XRef">
5.9</A>
, which summarize the features of the logic cells used by the various FPGA vendors. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=94497">
</A>
TABLE 5.4 <A NAME="38399">
</A>
Logic cell tables.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFirst">
<A NAME="pgfId=94507">
</A>
<SPAN CLASS="TableHeads">
Programmable ASIC family</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=94511">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFirst">
<A NAME="pgfId=94513">
</A>
<SPAN CLASS="TableHeads">
Programmable ASIC family</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94520">
</A>
<A HREF="CH05.5.htm#29099" CLASS="XRef">
Table 5.5</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94522">
</A>
Actel (ACT 1)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=94523">
</A>
Xilinx (XC3000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=94524">
</A>
Actel (ACT 2)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=94525">
</A>
Xilinx (XC4000)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94527">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94532">
</A>
<A HREF="CH05.5.htm#30912" CLASS="XRef">
Table 5.8</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94534">
</A>
Actel (ACT 3)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=94535">
</A>
Xilinx LCA (XC5200)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=94536">
</A>
Altera FLEX (8000/10k)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94541">
</A>
<A HREF="CH05.5.htm#23352" CLASS="XRef">
Table 5.6</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94543">
</A>
Altera MAX (EPM 5000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=94544">
</A>
Xilinx EPLD (XC7200/7300)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=94545">
</A>
QuickLogic (pASIC 1)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94547">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94552">
</A>
<A HREF="CH05.5.htm#40602" CLASS="XRef">
Table 5.9</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94554">
</A>
AMD MACH 5</P>
<P CLASS="TableLeft">
<A NAME="pgfId=94555">
</A>
Actel 3200DX</P>
<P CLASS="TableLeft">
<A NAME="pgfId=94556">
</A>
Altera MAX (EPM 9000)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94561">
</A>
<A HREF="CH05.5.htm#24904" CLASS="XRef">
Table 5.7</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94563">
</A>
Crosspoint (CP20K)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=94564">
</A>
Altera MAX (EPM 7000)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=94565">
</A>
Atmel (AT6000)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94567">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94569">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=94571">
</A>
</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=72752">
</A>
TABLE 5.5 <A NAME="29099">
</A>
Logic cells used by programmable ASICs.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72762">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72764">
</A>
<SPAN CLASS="TableHeads">
Actel ACT 1</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72766">
</A>
<SPAN CLASS="TableHeads">
Xilinx XC3000</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72768">
</A>
<SPAN CLASS="TableHeads">
Actel ACT 2</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72770">
</A>
<SPAN CLASS="TableHeads">
Xilinx XC4000</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72772">
</A>
<SPAN CLASS="TableHeads">
Basic<BR>
logic cell</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72774">
</A>
Logic module (LM)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72776">
</A>
CLB (Configurable Logic Block)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72778">
</A>
C-Module (combinatorial-module) and S-Module (sequential module)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72780">
</A>
CLB (Configurable Logic Block)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72782">
</A>
<SPAN CLASS="TableHeads">
Logic cell<BR>
contents</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72784">
</A>
Three 2:1MUXes plus OR gate</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72786">
</A>
32-bit LUT, 2 D flip-flops, 9 MUXes</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72788">
</A>
C-Module: 4:1 MUX, 2-input OR, 2-input AND</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72789">
</A>
S-Module: 4-input MUX, 2-input OR, latch or D flip-flop</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72791">
</A>
32-bit LUT, 2 D flip-flops, 10 MUXes, including fast carry logic</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72792">
</A>
E-suffix parts contain dual-port RAM.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72794">
</A>
<SPAN CLASS="TableHeads">
Logic path <BR>
delay</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72796">
</A>
Fixed</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72798">
</A>
Fixed with ability to bypass FF</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72800">
</A>
Fixed</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72802">
</A>
Fixed with ability to bypass FF</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72804">
</A>
<SPAN CLASS="TableHeads">
Combinational logic<BR>
functions</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72806">
</A>
Most 3-input, many 4-input functions (total 702 macros)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72808">
</A>
All 5-input functions plus 2 D flip-flops</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72810">
</A>
Most 3- and 4-input functions (total 766 macros)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72812">
</A>
Two 4-input LUTs plus combiner with ninth input</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72813">
</A>
CLB as 32-bit SRAM (except D-suffix parts)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72815">
</A>
<SPAN CLASS="TableHeads">
Flip-flop (FF)</SPAN>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72816">
</A>
<SPAN CLASS="TableHeads">
implementation</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72818">
</A>
1 LM required for latch, 2 LMs required for flip-flops</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72820">
</A>
2 D-flip-flops per CLB, latches can be built from pre-FF logic.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72822">
</A>
1 S-Module per D flip-flop; some FFs require 2 modules.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72824">
</A>
2 D flip-flops per CLB</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72826">
</A>
<SPAN CLASS="TableHeads">
Basic logic cells<BR>
in each chip</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72828">
</A>
LMs:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=91167">
</A>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72829">
</A>
A1010: 352 (8R <SPAN CLASS="Symbol">
¥</SPAN>
44C)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72830">
</A>
= 295 + 57 I/O </P>
<P CLASS="TableLeft">
<A NAME="pgfId=91168">
</A>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72831">
</A>
A1020: 616 (14 R<SPAN CLASS="Symbol">
¥</SPAN>
44C)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72832">
</A>
= 547 + 69 I/O</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72834">
</A>
64 (XC3020/A/L, XC3120/A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72835">
</A>
100 (XC3030/A/L, XC3130/A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72836">
</A>
144 (XC3042/A/L, XC3142/A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72837">
</A>
224 (XC3064/A/L, XC3164/A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72838">
</A>
320 (XC3090/A/L, XC3190/A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72839">
</A>
484 (XC3195/A)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72841">
</A>
A1225:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72842">
</A>
451 = 231 S + 220 C</P>
<P CLASS="TableLeft">
<A NAME="pgfId=91165">
</A>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72843">
</A>
A1240:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72844">
</A>
684 = 348 S + 336 C</P>
<P CLASS="TableLeft">
<A NAME="pgfId=91166">
</A>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72845">
</A>
A1280:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72846">
</A>
1232 = 624 S + 608 C</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=72848">
</A>
64 (XC4002A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72849">
</A>
100 (XC4003/A/E/H)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72850">
</A>
144 (XC4004A)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72851">
</A>
196 (XC4005/A/E/H)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72852">
</A>
256 (XC4006/E)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72853">
</A>
324 (XC4008/E)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72854">
</A>
400 (XC4010/D/E)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72855">
</A>
576 (XC4013/D/E)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72856">
</A>
784 (XC4020/E)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=72857">
</A>
1024 (XC4025/E)</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=72861">
</A>
TABLE 5.6 <A NAME="23352">
</A>
Logic cells used by programmable ASICs.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72869">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72871">
</A>
<SPAN CLASS="TableHeads">
Altera MAX 5000</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=72873">
</A>
<SPAN CLASS="TableHeads">
Xilinx XC7200/7300</SPAN>
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -